^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * These power domain indices match the numbers of the interrupt bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * representing the power areas in the various Interrupt Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * (e.g. SYSCISR, Interrupt Status Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A77995_PD_CA53_CPU0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A77995_PD_CA53_SCU 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Always-on power area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A77995_PD_ALWAYS_ON 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */