Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2018 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2018 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * These power domain indices match the numbers of the interrupt bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * representing the power areas in the various Interrupt Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * (e.g. SYSCISR, Interrupt Status Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A77980_PD_A2SC2		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A77980_PD_A2SC3		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A77980_PD_A2SC4		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A77980_PD_A2DP0		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A77980_PD_A2DP1		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A77980_PD_CA53_CPU0		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A77980_PD_CA53_CPU1		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A77980_PD_CA53_CPU2		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A77980_PD_CA53_CPU3		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A77980_PD_A2CN		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A77980_PD_A3VIP0		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A77980_PD_A2IR5		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A77980_PD_CR7			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A77980_PD_A2IR4		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A77980_PD_CA53_SCU		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A77980_PD_A2IR0		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A77980_PD_A3IR		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A77980_PD_A3VIP1		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A77980_PD_A3VIP2		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A77980_PD_A2IR1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R8A77980_PD_A2IR2		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R8A77980_PD_A2IR3		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R8A77980_PD_A2SC0		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R8A77980_PD_A2SC1		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Always-on power area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R8A77980_PD_ALWAYS_ON		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */