Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2016 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * These power domain indices match the numbers of the interrupt bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * representing the power areas in the various Interrupt Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * (e.g. SYSCISR, Interrupt Status Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R8A7795_PD_CA57_CPU0		 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R8A7795_PD_CA57_CPU1		 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A7795_PD_CA57_CPU2		 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A7795_PD_CA57_CPU3		 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A7795_PD_CA53_CPU0		 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A7795_PD_CA53_CPU1		 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R8A7795_PD_CA53_CPU2		 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R8A7795_PD_CA53_CPU3		 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A7795_PD_A3VP			 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R8A7795_PD_CA57_SCU		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R8A7795_PD_CR7			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R8A7795_PD_A3VC			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R8A7795_PD_3DG_A		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R8A7795_PD_3DG_B		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R8A7795_PD_3DG_C		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R8A7795_PD_3DG_D		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R8A7795_PD_CA53_SCU		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R8A7795_PD_3DG_E		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R8A7795_PD_A3IR			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R8A7795_PD_A2VC0		25	/* ES1.x only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R8A7795_PD_A2VC1		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Always-on power area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R8A7795_PD_ALWAYS_ON		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */