Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2018 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __DT_BINDINGS_POWER_R8A7744_SYSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __DT_BINDINGS_POWER_R8A7744_SYSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * These power domain indices match the numbers of the interrupt bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * representing the power areas in the various Interrupt Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * (e.g. SYSCISR, Interrupt Status Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * Note that RZ/G1N is identical to RZ/G2M w.r.t. power domains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R8A7744_PD_CA15_CPU0		 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R8A7744_PD_CA15_CPU1		 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R8A7744_PD_CA15_SCU		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R8A7744_PD_SGX			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Always-on power area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R8A7744_PD_ALWAYS_ON		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif /* __DT_BINDINGS_POWER_R8A7744_SYSC_H__ */