^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define _DT_BINDINGS_POWER_QCOM_RPMPD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* SDM845 Power Domain Indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define SDM845_EBI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SDM845_MX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SDM845_MX_AO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SDM845_CX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SDM845_CX_AO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SDM845_LMX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SDM845_LCX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SDM845_GFX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SDM845_MSS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* SM8150 Power Domain Indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SM8150_MSS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SM8150_EBI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SM8150_LMX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SM8150_LCX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SM8150_GFX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SM8150_MX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SM8150_MX_AO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SM8150_CX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SM8150_CX_AO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SM8150_MMCX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SM8150_MMCX_AO 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* SM8250 Power Domain Indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SM8250_CX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SM8250_CX_AO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SM8250_EBI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SM8250_GFX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SM8250_LCX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SM8250_LMX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SM8250_MMCX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SM8250_MMCX_AO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SM8250_MX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SM8250_MX_AO 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* SC7180 Power Domain Indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC7180_CX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SC7180_CX_AO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SC7180_GFX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC7180_MX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC7180_MX_AO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC7180_LMX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC7180_LCX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC7180_MSS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* SDM845 Power Domain performance levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RPMH_REGULATOR_LEVEL_RETENTION 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RPMH_REGULATOR_LEVEL_MIN_SVS 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RPMH_REGULATOR_LEVEL_LOW_SVS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RPMH_REGULATOR_LEVEL_SVS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RPMH_REGULATOR_LEVEL_SVS_L0 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RPMH_REGULATOR_LEVEL_SVS_L1 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RPMH_REGULATOR_LEVEL_SVS_L2 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RPMH_REGULATOR_LEVEL_NOM 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RPMH_REGULATOR_LEVEL_NOM_L1 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RPMH_REGULATOR_LEVEL_NOM_L2 336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RPMH_REGULATOR_LEVEL_TURBO 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RPMH_REGULATOR_LEVEL_TURBO_L1 416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* MSM8976 Power Domain Indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MSM8976_VDDCX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MSM8976_VDDCX_AO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MSM8976_VDDCX_VFL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MSM8976_VDDMX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MSM8976_VDDMX_AO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MSM8976_VDDMX_VFL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* MSM8996 Power Domain Indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MSM8996_VDDCX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MSM8996_VDDCX_AO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MSM8996_VDDCX_VFC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MSM8996_VDDMX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MSM8996_VDDMX_AO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MSM8996_VDDSSCX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MSM8996_VDDSSCX_VFC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* MSM8998 Power Domain Indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MSM8998_VDDCX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MSM8998_VDDCX_AO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MSM8998_VDDCX_VFL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MSM8998_VDDMX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MSM8998_VDDMX_AO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MSM8998_VDDMX_VFL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MSM8998_SSCCX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MSM8998_SSCCX_VFL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MSM8998_SSCMX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MSM8998_SSCMX_VFL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* QCS404 Power Domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QCS404_VDDMX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define QCS404_VDDMX_AO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define QCS404_VDDMX_VFL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define QCS404_LPICX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QCS404_LPICX_VFL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QCS404_LPIMX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QCS404_LPIMX_VFL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* RPM SMD Power Domain performance levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RPM_SMD_LEVEL_RETENTION 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RPM_SMD_LEVEL_RETENTION_PLUS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RPM_SMD_LEVEL_MIN_SVS 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RPM_SMD_LEVEL_LOW_SVS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RPM_SMD_LEVEL_SVS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RPM_SMD_LEVEL_SVS_PLUS 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RPM_SMD_LEVEL_NOM 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RPM_SMD_LEVEL_NOM_PLUS 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RPM_SMD_LEVEL_TURBO 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RPM_SMD_LEVEL_TURBO_NO_CPR 416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RPM_SMD_LEVEL_TURBO_HIGH 448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RPM_SMD_LEVEL_BINNING 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags