^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __DT_BINDINGS_POWER_PX30_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __DT_BINDINGS_POWER_PX30_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* VD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define PX30_PD_A35_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define PX30_PD_A35_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define PX30_PD_A35_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define PX30_PD_A35_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PX30_PD_SCU 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* VD_LOGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PX30_PD_USB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PX30_PD_DDR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PX30_PD_SDCARD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PX30_PD_CRYPTO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PX30_PD_GMAC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PX30_PD_MMC_NAND 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PX30_PD_VPU 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PX30_PD_VO 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PX30_PD_VI 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PX30_PD_GPU 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* VD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PX30_PD_PMU 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif