^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Actions Semi S900 SPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef DT_BINDINGS_POWER_OWL_S900_POWERGATE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define DT_BINDINGS_POWER_OWL_S900_POWERGATE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define S900_PD_GPU_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define S900_PD_VCE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define S900_PD_SENSOR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define S900_PD_VDE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S900_PD_HDE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S900_PD_USB3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S900_PD_DDR0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S900_PD_DDR1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S900_PD_DE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S900_PD_NAND 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S900_PD_USB2_H0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S900_PD_USB2_H1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif