^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2017 Andreas Färber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef DT_BINDINGS_POWER_OWL_S500_POWERGATE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define DT_BINDINGS_POWER_OWL_S500_POWERGATE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define S500_PD_VDE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define S500_PD_VCE_SI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define S500_PD_USB2_1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define S500_PD_CPU2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define S500_PD_CPU3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S500_PD_DMA 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S500_PD_DS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S500_PD_USB3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S500_PD_USB2_0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif