^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_POWER_MT2712_POWER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_POWER_MT2712_POWER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MT2712_POWER_DOMAIN_MM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MT2712_POWER_DOMAIN_VDEC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MT2712_POWER_DOMAIN_VENC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MT2712_POWER_DOMAIN_ISP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MT2712_POWER_DOMAIN_AUDIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MT2712_POWER_DOMAIN_USB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MT2712_POWER_DOMAIN_USB2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MT2712_POWER_DOMAIN_MFG 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MT2712_POWER_DOMAIN_MFG_SC1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT2712_POWER_DOMAIN_MFG_SC2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MT2712_POWER_DOMAIN_MFG_SC3 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */