^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung's Exynos pinctrl bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Krzysztof Kozlowski <krzk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define EXYNOS_PIN_PULL_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define EXYNOS_PIN_PULL_DOWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define EXYNOS_PIN_PULL_UP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C64XX_PIN_PULL_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C64XX_PIN_PULL_DOWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C64XX_PIN_PULL_UP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Pin function in power down mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EXYNOS_PIN_PDN_OUT0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EXYNOS_PIN_PDN_OUT1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EXYNOS_PIN_PDN_INPUT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EXYNOS_PIN_PDN_PREV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EXYNOS4_PIN_DRV_LV1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EXYNOS4_PIN_DRV_LV2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EXYNOS4_PIN_DRV_LV3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EXYNOS4_PIN_DRV_LV4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Drive strengths for Exynos5260 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EXYNOS5260_PIN_DRV_LV1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EXYNOS5260_PIN_DRV_LV2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EXYNOS5260_PIN_DRV_LV4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EXYNOS5260_PIN_DRV_LV6 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EXYNOS5420_PIN_DRV_LV1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EXYNOS5420_PIN_DRV_LV2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EXYNOS5420_PIN_DRV_LV3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXYNOS5420_PIN_DRV_LV4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Drive strengths for Exynos5433 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EXYNOS5433_PIN_DRV_FAST_SR1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EXYNOS5433_PIN_DRV_FAST_SR2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EXYNOS5433_PIN_DRV_FAST_SR3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EXYNOS5433_PIN_DRV_FAST_SR4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EXYNOS5433_PIN_DRV_FAST_SR5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EXYNOS5433_PIN_DRV_FAST_SR6 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EXYNOS5433_PIN_DRV_SLOW_SR1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EXYNOS5433_PIN_DRV_SLOW_SR2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EXYNOS_PIN_FUNC_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EXYNOS_PIN_FUNC_OUTPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EXYNOS_PIN_FUNC_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EXYNOS_PIN_FUNC_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EXYNOS_PIN_FUNC_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EXYNOS_PIN_FUNC_5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EXYNOS_PIN_FUNC_6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EXYNOS_PIN_FUNC_EINT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Drive strengths for Exynos7 FSYS1 block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EXYNOS7_FSYS1_PIN_DRV_LV1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EXYNOS7_FSYS1_PIN_DRV_LV2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EXYNOS7_FSYS1_PIN_DRV_LV3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EXYNOS7_FSYS1_PIN_DRV_LV4 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EXYNOS7_FSYS1_PIN_DRV_LV5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EXYNOS7_FSYS1_PIN_DRV_LV6 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags