^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Defines macros and constants for Renesas RZ/N1 pin controller pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * muxing functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DT_BINDINGS_RZN1_PINCTRL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DT_BINDINGS_RZN1_PINCTRL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RZN1_PINMUX(_gpio, _func) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) (((_func) << 8) | (_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Given the different levels of muxing on the SoC, it was decided to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * muxes are all represented by one single value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * You can derive the hardware value pretty easily too, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 0...9 are Level 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 10...71 are Level 2. The Level 2 mux will be set to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * set accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 72...103 are for the 2 MDIO muxes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RZN1_FUNC_HIGHZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RZN1_FUNC_0L 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RZN1_FUNC_CLK_ETH_NAND 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RZN1_FUNC_QSPI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RZN1_FUNC_SDIO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RZN1_FUNC_LCD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RZN1_FUNC_LCD_E 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RZN1_FUNC_MSEBIM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RZN1_FUNC_MSEBIS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif /* __DT_BINDINGS_RZN1_PINCTRL_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags