Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Defines macros and constants for Renesas RZ/A2 pin controller pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * muxing functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define RZA2_PINS_PER_PORT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Port names as labeled in the Hardware Manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PORT0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PORT1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PORT2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PORT3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PORT4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PORT5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PORT6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PORT7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PORT8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PORT9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PORTA 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PORTB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PORTC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PORTD 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PORTE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PORTF 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PORTG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PORTH 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* No I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PORTJ 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PORTK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PORTL 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PORTM 21	/* Pins PM_0/1 are labeled JP_0/1 in HW manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * Create the pin index from its bank and position numbers and store in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * the upper 16 bits the alternate function identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RZA2_PINMUX(b, p, f)	((b) * RZA2_PINS_PER_PORT + (p) | (f << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  * Convert a port and pin label to its global pin index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  #define RZA2_PIN(port, pin)	((port) * RZA2_PINS_PER_PORT + (pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */