^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Defines macros and constants for Renesas RZ/A1 pin controller pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * muxing functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RZA1_PINS_PER_PORT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Create the pin index from its bank and position numbers and store in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * the upper 16 bits the alternate function identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RZA1_PINMUX(b, p, f) ((b) * RZA1_PINS_PER_PORT + (p) | (f << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */