^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This header provides constants for the Qualcomm PMIC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Multi-Purpose Pin binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* power-source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Digital Input/Output: level [PM8058] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PM8058_MPP_VPH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PM8058_MPP_S3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PM8058_MPP_L2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PM8058_MPP_L3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Digital Input/Output: level [PM8901] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PM8901_MPP_MSMIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PM8901_MPP_DIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PM8901_MPP_L5 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PM8901_MPP_S4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PM8901_MPP_VPH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Digital Input/Output: level [PM8921] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PM8921_MPP_S4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PM8921_MPP_L15 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PM8921_MPP_L17 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PM8921_MPP_VPH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Digital Input/Output: level [PM8821] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PM8821_MPP_1P8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PM8821_MPP_VPH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Digital Input/Output: level [PM8018] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PM8018_MPP_L4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PM8018_MPP_L14 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PM8018_MPP_S3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PM8018_MPP_L6 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PM8018_MPP_L2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PM8018_MPP_L5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PM8018_MPP_VPH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Digital Input/Output: level [PM8038] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PM8038_MPP_L20 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PM8038_MPP_L11 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PM8038_MPP_L5 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PM8038_MPP_L15 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PM8038_MPP_L17 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PM8038_MPP_VPH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PM8841_MPP_VPH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PM8841_MPP_S3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PM8916_MPP_VPH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PM8916_MPP_L2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PM8916_MPP_L5 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PM8941_MPP_VPH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PM8941_MPP_L1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PM8941_MPP_S3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PM8941_MPP_L6 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PMA8084_MPP_VPH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PMA8084_MPP_L1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PMA8084_MPP_S4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PMA8084_MPP_L6 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PM8994_MPP_VPH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Only supported for MPP_05-MPP_08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PM8994_MPP_L19 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PM8994_MPP_S4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PM8994_MPP_L12 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Analog Input - Set the source for analog input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * To be used with "qcom,amux-route" property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PMIC_MPP_AMUX_ROUTE_CH5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PMIC_MPP_AMUX_ROUTE_CH6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PMIC_MPP_AMUX_ROUTE_CH7 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PMIC_MPP_AMUX_ROUTE_CH8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PMIC_MPP_AMUX_ROUTE_ABUS1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PMIC_MPP_AMUX_ROUTE_ABUS2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PMIC_MPP_AMUX_ROUTE_ABUS3 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PMIC_MPP_AMUX_ROUTE_ABUS4 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Analog Output: level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PMIC_MPP_AOUT_LVL_1V25 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PMIC_MPP_AOUT_LVL_1V25_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PMIC_MPP_AOUT_LVL_0V625 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PMIC_MPP_AOUT_LVL_0V3125 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PMIC_MPP_AOUT_LVL_MPP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PMIC_MPP_AOUT_LVL_ABUS1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PMIC_MPP_AOUT_LVL_ABUS2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PMIC_MPP_AOUT_LVL_ABUS3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* To be used with "function" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PMIC_MPP_FUNC_NORMAL "normal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PMIC_MPP_FUNC_PAIRED "paired"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PMIC_MPP_FUNC_DTEST1 "dtest1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PMIC_MPP_FUNC_DTEST2 "dtest2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PMIC_MPP_FUNC_DTEST3 "dtest3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PMIC_MPP_FUNC_DTEST4 "dtest4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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