Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides constants for Tegra pinctrl bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _DT_BINDINGS_PINCTRL_TEGRA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Enable/disable for diffeent dt properties. This is applicable for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA_PIN_DISABLE				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA_PIN_ENABLE				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA_PIN_PULL_NONE				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA_PIN_PULL_DOWN				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA_PIN_PULL_UP				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Low power mode driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA_PIN_LP_DRIVE_DIV_8			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA_PIN_LP_DRIVE_DIV_4			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA_PIN_LP_DRIVE_DIV_2			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_PIN_LP_DRIVE_DIV_1			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Rising/Falling slew rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA_PIN_SLEW_RATE_FASTEST			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA_PIN_SLEW_RATE_FAST			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA_PIN_SLEW_RATE_SLOW			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA_PIN_SLEW_RATE_SLOWEST			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif