^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * pinctrl bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Aapo Vienamo <avienamo@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Voltage levels of the I/O pad's source rail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA_IO_PAD_VOLTAGE_1V8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA_IO_PAD_VOLTAGE_3V3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #endif