^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017~2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _IMX8QM_PADS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _IMX8QM_PADS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* pin id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX8QM_SIM0_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX8QM_SIM0_RST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX8QM_SIM0_IO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX8QM_SIM0_PD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX8QM_SIM0_POWER_EN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX8QM_SIM0_GPIO0_00 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SIM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX8QM_M40_I2C0_SCL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX8QM_M40_I2C0_SDA 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX8QM_M40_GPIO0_00 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX8QM_M40_GPIO0_01 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX8QM_M41_I2C0_SCL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX8QM_M41_I2C0_SDA 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX8QM_M41_GPIO0_00 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX8QM_M41_GPIO0_01 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX8QM_GPT0_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX8QM_GPT0_CAPTURE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX8QM_GPT0_COMPARE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX8QM_GPT1_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX8QM_GPT1_CAPTURE 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX8QM_GPT1_COMPARE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX8QM_UART0_RX 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX8QM_UART0_TX 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX8QM_UART0_RTS_B 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX8QM_UART0_CTS_B 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX8QM_UART1_TX 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX8QM_UART1_RX 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX8QM_UART1_RTS_B 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX8QM_UART1_CTS_B 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX8QM_SCU_PMIC_MEMC_ON 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX8QM_SCU_WDOG_OUT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX8QM_PMIC_I2C_SDA 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX8QM_PMIC_I2C_SCL 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX8QM_PMIC_EARLY_WARNING 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX8QM_PMIC_INT_B 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX8QM_SCU_GPIO0_00 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX8QM_SCU_GPIO0_01 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX8QM_SCU_GPIO0_02 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX8QM_SCU_GPIO0_03 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX8QM_SCU_GPIO0_04 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX8QM_SCU_GPIO0_05 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX8QM_SCU_GPIO0_06 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX8QM_SCU_GPIO0_07 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX8QM_SCU_BOOT_MODE0 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX8QM_SCU_BOOT_MODE1 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX8QM_SCU_BOOT_MODE2 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX8QM_SCU_BOOT_MODE3 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX8QM_SCU_BOOT_MODE4 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX8QM_SCU_BOOT_MODE5 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX8QM_LVDS0_GPIO00 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX8QM_LVDS0_GPIO01 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX8QM_LVDS0_I2C0_SCL 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX8QM_LVDS0_I2C0_SDA 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX8QM_LVDS0_I2C1_SCL 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX8QM_LVDS0_I2C1_SDA 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX8QM_LVDS1_GPIO00 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX8QM_LVDS1_GPIO01 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX8QM_LVDS1_I2C0_SCL 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX8QM_LVDS1_I2C0_SDA 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX8QM_LVDS1_I2C1_SCL 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX8QM_LVDS1_I2C1_SDA 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX8QM_MIPI_DSI0_I2C0_SCL 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX8QM_MIPI_DSI0_I2C0_SDA 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX8QM_MIPI_DSI0_GPIO0_00 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX8QM_MIPI_DSI0_GPIO0_01 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX8QM_MIPI_DSI1_I2C0_SCL 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX8QM_MIPI_DSI1_I2C0_SDA 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX8QM_MIPI_DSI1_GPIO0_00 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX8QM_MIPI_DSI1_GPIO0_01 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX8QM_MIPI_CSI0_MCLK_OUT 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX8QM_MIPI_CSI0_I2C0_SCL 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX8QM_MIPI_CSI0_I2C0_SDA 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX8QM_MIPI_CSI0_GPIO0_00 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX8QM_MIPI_CSI0_GPIO0_01 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX8QM_MIPI_CSI1_MCLK_OUT 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX8QM_MIPI_CSI1_GPIO0_00 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX8QM_MIPI_CSI1_GPIO0_01 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX8QM_MIPI_CSI1_I2C0_SCL 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX8QM_MIPI_CSI1_I2C0_SDA 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX8QM_HDMI_TX0_TS_SCL 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX8QM_HDMI_TX0_TS_SDA 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX8QM_COMP_CTL_GPIO_3V3_HDMIGPIO 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX8QM_ESAI1_FSR 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX8QM_ESAI1_FST 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX8QM_ESAI1_SCKR 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX8QM_ESAI1_SCKT 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX8QM_ESAI1_TX0 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX8QM_ESAI1_TX1 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX8QM_ESAI1_TX2_RX3 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX8QM_ESAI1_TX3_RX2 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX8QM_ESAI1_TX4_RX1 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX8QM_ESAI1_TX5_RX0 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX8QM_SPDIF0_RX 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX8QM_SPDIF0_TX 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX8QM_SPDIF0_EXT_CLK 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX8QM_SPI3_SCK 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX8QM_SPI3_SDO 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX8QM_SPI3_SDI 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX8QM_SPI3_CS0 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX8QM_SPI3_CS1 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX8QM_ESAI0_FSR 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX8QM_ESAI0_FST 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX8QM_ESAI0_SCKR 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX8QM_ESAI0_SCKT 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX8QM_ESAI0_TX0 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX8QM_ESAI0_TX1 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX8QM_ESAI0_TX2_RX3 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX8QM_ESAI0_TX3_RX2 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX8QM_ESAI0_TX4_RX1 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX8QM_ESAI0_TX5_RX0 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX8QM_MCLK_IN0 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX8QM_MCLK_OUT0 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX8QM_SPI0_SCK 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX8QM_SPI0_SDO 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX8QM_SPI0_SDI 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX8QM_SPI0_CS0 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX8QM_SPI0_CS1 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX8QM_SPI2_SCK 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX8QM_SPI2_SDO 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX8QM_SPI2_SDI 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX8QM_SPI2_CS0 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX8QM_SPI2_CS1 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX8QM_SAI1_RXC 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX8QM_SAI1_RXD 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX8QM_SAI1_RXFS 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX8QM_SAI1_TXC 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX8QM_SAI1_TXD 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX8QM_SAI1_TXFS 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX8QM_ADC_IN7 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX8QM_ADC_IN6 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX8QM_ADC_IN5 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX8QM_ADC_IN4 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX8QM_ADC_IN3 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX8QM_ADC_IN2 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX8QM_ADC_IN1 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX8QM_ADC_IN0 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX8QM_MLB_SIG 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX8QM_MLB_CLK 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX8QM_MLB_DATA 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX8QM_FLEXCAN0_RX 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX8QM_FLEXCAN0_TX 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX8QM_FLEXCAN1_RX 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX8QM_FLEXCAN1_TX 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX8QM_FLEXCAN2_RX 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX8QM_FLEXCAN2_TX 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX8QM_USB_SS3_TC0 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX8QM_USB_SS3_TC1 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX8QM_USB_SS3_TC2 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX8QM_USB_SS3_TC3 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX8QM_COMP_CTL_GPIO_3V3_USB3IO 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX8QM_USDHC1_RESET_B 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX8QM_USDHC1_VSELECT 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX8QM_USDHC2_RESET_B 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX8QM_USDHC2_VSELECT 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX8QM_USDHC2_WP 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX8QM_USDHC2_CD_B 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX8QM_ENET0_MDIO 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX8QM_ENET0_MDC 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX8QM_ENET0_REFCLK_125M_25M 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX8QM_ENET1_REFCLK_125M_25M 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX8QM_ENET1_MDIO 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX8QM_ENET1_MDC 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX8QM_QSPI1A_SS0_B 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX8QM_QSPI1A_SS1_B 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX8QM_QSPI1A_SCLK 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX8QM_QSPI1A_DQS 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX8QM_QSPI1A_DATA3 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX8QM_QSPI1A_DATA2 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX8QM_QSPI1A_DATA1 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX8QM_QSPI1A_DATA0 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI1 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX8QM_QSPI0A_DATA0 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX8QM_QSPI0A_DATA1 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX8QM_QSPI0A_DATA2 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX8QM_QSPI0A_DATA3 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX8QM_QSPI0A_DQS 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX8QM_QSPI0A_SS0_B 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX8QM_QSPI0A_SS1_B 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX8QM_QSPI0A_SCLK 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX8QM_QSPI0B_SCLK 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX8QM_QSPI0B_DATA0 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX8QM_QSPI0B_DATA1 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX8QM_QSPI0B_DATA2 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX8QM_QSPI0B_DATA3 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX8QM_QSPI0B_DQS 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX8QM_QSPI0B_SS0_B 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX8QM_QSPI0B_SS1_B 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI0 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX8QM_PCIE_CTRL0_CLKREQ_B 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX8QM_PCIE_CTRL0_WAKE_B 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX8QM_PCIE_CTRL0_PERST_B 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX8QM_PCIE_CTRL1_CLKREQ_B 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX8QM_PCIE_CTRL1_WAKE_B 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX8QM_PCIE_CTRL1_PERST_B 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX8QM_USB_HSIC0_DATA 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMX8QM_USB_HSIC0_STROBE 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX8QM_CALIBRATION_0_HSIC 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IMX8QM_CALIBRATION_1_HSIC 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX8QM_EMMC0_CLK 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IMX8QM_EMMC0_CMD 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX8QM_EMMC0_DATA0 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IMX8QM_EMMC0_DATA1 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX8QM_EMMC0_DATA2 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMX8QM_EMMC0_DATA3 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX8QM_EMMC0_DATA4 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IMX8QM_EMMC0_DATA5 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX8QM_EMMC0_DATA6 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMX8QM_EMMC0_DATA7 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX8QM_EMMC0_STROBE 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMX8QM_EMMC0_RESET_B 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMX8QM_USDHC1_CLK 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX8QM_USDHC1_CMD 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMX8QM_USDHC1_DATA0 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMX8QM_USDHC1_DATA1 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMX8QM_CTL_NAND_RE_P_N 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX8QM_USDHC1_DATA2 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IMX8QM_USDHC1_DATA3 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX8QM_CTL_NAND_DQS_P_N 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IMX8QM_USDHC1_DATA4 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX8QM_USDHC1_DATA5 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IMX8QM_USDHC1_DATA6 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMX8QM_USDHC1_DATA7 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMX8QM_USDHC1_STROBE 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL2 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IMX8QM_USDHC2_CLK 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX8QM_USDHC2_CMD 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IMX8QM_USDHC2_DATA0 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IMX8QM_USDHC2_DATA1 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IMX8QM_USDHC2_DATA2 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX8QM_USDHC2_DATA3 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL3 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX8QM_ENET0_RGMII_TXC 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IMX8QM_ENET0_RGMII_TX_CTL 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX8QM_ENET0_RGMII_TXD0 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IMX8QM_ENET0_RGMII_TXD1 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX8QM_ENET0_RGMII_TXD2 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IMX8QM_ENET0_RGMII_TXD3 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX8QM_ENET0_RGMII_RXC 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IMX8QM_ENET0_RGMII_RX_CTL 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IMX8QM_ENET0_RGMII_RXD0 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IMX8QM_ENET0_RGMII_RXD1 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IMX8QM_ENET0_RGMII_RXD2 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IMX8QM_ENET0_RGMII_RXD3 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IMX8QM_ENET1_RGMII_TXC 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX8QM_ENET1_RGMII_TX_CTL 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMX8QM_ENET1_RGMII_TXD0 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX8QM_ENET1_RGMII_TXD1 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMX8QM_ENET1_RGMII_TXD2 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IMX8QM_ENET1_RGMII_TXD3 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IMX8QM_ENET1_RGMII_RXC 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IMX8QM_ENET1_RGMII_RX_CTL 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IMX8QM_ENET1_RGMII_RXD0 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IMX8QM_ENET1_RGMII_RXD1 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IMX8QM_ENET1_RGMII_RXD2 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IMX8QM_ENET1_RGMII_RXD3 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * format: <pin_id mux_mode>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IMX8QM_SIM0_CLK_DMA_SIM0_CLK IMX8QM_SIM0_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 IMX8QM_SIM0_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IMX8QM_SIM0_RST_DMA_SIM0_RST IMX8QM_SIM0_RST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 IMX8QM_SIM0_RST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IMX8QM_SIM0_IO_DMA_SIM0_IO IMX8QM_SIM0_IO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 IMX8QM_SIM0_IO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IMX8QM_SIM0_PD_DMA_SIM0_PD IMX8QM_SIM0_PD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IMX8QM_SIM0_PD_DMA_I2C3_SCL IMX8QM_SIM0_PD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IMX8QM_SIM0_PD_LSIO_GPIO0_IO03 IMX8QM_SIM0_PD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN IMX8QM_SIM0_POWER_EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA IMX8QM_SIM0_POWER_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IMX8QM_SIM0_POWER_EN_LSIO_GPIO0_IO04 IMX8QM_SIM0_POWER_EN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IMX8QM_SIM0_GPIO0_00_DMA_SIM0_POWER_EN IMX8QM_SIM0_GPIO0_00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 IMX8QM_SIM0_GPIO0_00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IMX8QM_M40_I2C0_SCL_M40_I2C0_SCL IMX8QM_M40_I2C0_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IMX8QM_M40_I2C0_SCL_M40_UART0_RX IMX8QM_M40_I2C0_SCL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IMX8QM_M40_I2C0_SCL_M40_GPIO0_IO02 IMX8QM_M40_I2C0_SCL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06 IMX8QM_M40_I2C0_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IMX8QM_M40_I2C0_SDA_M40_I2C0_SDA IMX8QM_M40_I2C0_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IMX8QM_M40_I2C0_SDA_M40_UART0_TX IMX8QM_M40_I2C0_SDA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IMX8QM_M40_I2C0_SDA_M40_GPIO0_IO03 IMX8QM_M40_I2C0_SDA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07 IMX8QM_M40_I2C0_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IMX8QM_M40_GPIO0_00_M40_GPIO0_IO00 IMX8QM_M40_GPIO0_00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IMX8QM_M40_GPIO0_00_M40_TPM0_CH0 IMX8QM_M40_GPIO0_00 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IMX8QM_M40_GPIO0_00_DMA_UART4_RX IMX8QM_M40_GPIO0_00 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08 IMX8QM_M40_GPIO0_00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IMX8QM_M40_GPIO0_01_M40_GPIO0_IO01 IMX8QM_M40_GPIO0_01 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IMX8QM_M40_GPIO0_01_M40_TPM0_CH1 IMX8QM_M40_GPIO0_01 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IMX8QM_M40_GPIO0_01_DMA_UART4_TX IMX8QM_M40_GPIO0_01 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09 IMX8QM_M40_GPIO0_01 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL IMX8QM_M41_I2C0_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IMX8QM_M41_I2C0_SCL_M41_UART0_RX IMX8QM_M41_I2C0_SCL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IMX8QM_M41_I2C0_SCL_M41_GPIO0_IO02 IMX8QM_M41_I2C0_SCL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10 IMX8QM_M41_I2C0_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA IMX8QM_M41_I2C0_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IMX8QM_M41_I2C0_SDA_M41_UART0_TX IMX8QM_M41_I2C0_SDA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IMX8QM_M41_I2C0_SDA_M41_GPIO0_IO03 IMX8QM_M41_I2C0_SDA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11 IMX8QM_M41_I2C0_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IMX8QM_M41_GPIO0_00_M41_GPIO0_IO00 IMX8QM_M41_GPIO0_00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IMX8QM_M41_GPIO0_00_M41_TPM0_CH0 IMX8QM_M41_GPIO0_00 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IMX8QM_M41_GPIO0_00_DMA_UART3_RX IMX8QM_M41_GPIO0_00 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12 IMX8QM_M41_GPIO0_00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IMX8QM_M41_GPIO0_01_M41_GPIO0_IO01 IMX8QM_M41_GPIO0_01 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IMX8QM_M41_GPIO0_01_M41_TPM0_CH1 IMX8QM_M41_GPIO0_01 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IMX8QM_M41_GPIO0_01_DMA_UART3_TX IMX8QM_M41_GPIO0_01 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13 IMX8QM_M41_GPIO0_01 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IMX8QM_GPT0_CLK_LSIO_GPT0_CLK IMX8QM_GPT0_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IMX8QM_GPT0_CLK_DMA_I2C1_SCL IMX8QM_GPT0_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IMX8QM_GPT0_CLK_LSIO_KPP0_COL4 IMX8QM_GPT0_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 IMX8QM_GPT0_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IMX8QM_GPT0_CAPTURE_LSIO_GPT0_CAPTURE IMX8QM_GPT0_CAPTURE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA IMX8QM_GPT0_CAPTURE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IMX8QM_GPT0_CAPTURE_LSIO_KPP0_COL5 IMX8QM_GPT0_CAPTURE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 IMX8QM_GPT0_CAPTURE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IMX8QM_GPT0_COMPARE_LSIO_GPT0_COMPARE IMX8QM_GPT0_COMPARE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT IMX8QM_GPT0_COMPARE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IMX8QM_GPT0_COMPARE_LSIO_KPP0_COL6 IMX8QM_GPT0_COMPARE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IMX8QM_GPT0_COMPARE_LSIO_GPIO0_IO16 IMX8QM_GPT0_COMPARE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IMX8QM_GPT1_CLK_LSIO_GPT1_CLK IMX8QM_GPT1_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IMX8QM_GPT1_CLK_DMA_I2C2_SCL IMX8QM_GPT1_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IMX8QM_GPT1_CLK_LSIO_KPP0_COL7 IMX8QM_GPT1_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IMX8QM_GPT1_CLK_LSIO_GPIO0_IO17 IMX8QM_GPT1_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IMX8QM_GPT1_CAPTURE_LSIO_GPT1_CAPTURE IMX8QM_GPT1_CAPTURE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA IMX8QM_GPT1_CAPTURE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IMX8QM_GPT1_CAPTURE_LSIO_KPP0_ROW4 IMX8QM_GPT1_CAPTURE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 IMX8QM_GPT1_CAPTURE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IMX8QM_GPT1_COMPARE_LSIO_GPT1_COMPARE IMX8QM_GPT1_COMPARE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT IMX8QM_GPT1_COMPARE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IMX8QM_GPT1_COMPARE_LSIO_KPP0_ROW5 IMX8QM_GPT1_COMPARE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 IMX8QM_GPT1_COMPARE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IMX8QM_UART0_RX_DMA_UART0_RX IMX8QM_UART0_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IMX8QM_UART0_RX_SCU_UART0_RX IMX8QM_UART0_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IMX8QM_UART0_RX_LSIO_GPIO0_IO20 IMX8QM_UART0_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define IMX8QM_UART0_TX_DMA_UART0_TX IMX8QM_UART0_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IMX8QM_UART0_TX_SCU_UART0_TX IMX8QM_UART0_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IMX8QM_UART0_TX_LSIO_GPIO0_IO21 IMX8QM_UART0_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IMX8QM_UART0_RTS_B_DMA_UART0_RTS_B IMX8QM_UART0_RTS_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT IMX8QM_UART0_RTS_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define IMX8QM_UART0_RTS_B_DMA_UART2_RX IMX8QM_UART0_RTS_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IMX8QM_UART0_RTS_B_LSIO_GPIO0_IO22 IMX8QM_UART0_RTS_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IMX8QM_UART0_CTS_B_DMA_UART0_CTS_B IMX8QM_UART0_CTS_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT IMX8QM_UART0_CTS_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IMX8QM_UART0_CTS_B_DMA_UART2_TX IMX8QM_UART0_CTS_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define IMX8QM_UART0_CTS_B_LSIO_GPIO0_IO23 IMX8QM_UART0_CTS_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define IMX8QM_UART1_TX_DMA_UART1_TX IMX8QM_UART1_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define IMX8QM_UART1_TX_DMA_SPI3_SCK IMX8QM_UART1_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define IMX8QM_UART1_TX_LSIO_GPIO0_IO24 IMX8QM_UART1_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IMX8QM_UART1_RX_DMA_UART1_RX IMX8QM_UART1_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define IMX8QM_UART1_RX_DMA_SPI3_SDO IMX8QM_UART1_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define IMX8QM_UART1_RX_LSIO_GPIO0_IO25 IMX8QM_UART1_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B IMX8QM_UART1_RTS_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define IMX8QM_UART1_RTS_B_DMA_SPI3_SDI IMX8QM_UART1_RTS_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B IMX8QM_UART1_RTS_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IMX8QM_UART1_RTS_B_LSIO_GPIO0_IO26 IMX8QM_UART1_RTS_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B IMX8QM_UART1_CTS_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define IMX8QM_UART1_CTS_B_DMA_SPI3_CS0 IMX8QM_UART1_CTS_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B IMX8QM_UART1_CTS_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define IMX8QM_UART1_CTS_B_LSIO_GPIO0_IO27 IMX8QM_UART1_CTS_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IMX8QM_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON IMX8QM_SCU_PMIC_MEMC_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IMX8QM_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT IMX8QM_SCU_WDOG_OUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IMX8QM_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QM_PMIC_I2C_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IMX8QM_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QM_PMIC_I2C_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define IMX8QM_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING IMX8QM_PMIC_EARLY_WARNING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define IMX8QM_PMIC_INT_B_SCU_DIMX8QMMIC_INT_B IMX8QM_PMIC_INT_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IMX8QM_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QM_SCU_GPIO0_00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define IMX8QM_SCU_GPIO0_00_SCU_UART0_RX IMX8QM_SCU_GPIO0_00 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IMX8QM_SCU_GPIO0_00_LSIO_GPIO0_IO28 IMX8QM_SCU_GPIO0_00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IMX8QM_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QM_SCU_GPIO0_01 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IMX8QM_SCU_GPIO0_01_SCU_UART0_TX IMX8QM_SCU_GPIO0_01 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IMX8QM_SCU_GPIO0_01_LSIO_GPIO0_IO29 IMX8QM_SCU_GPIO0_01 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IO02 IMX8QM_SCU_GPIO0_02 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON IMX8QM_SCU_GPIO0_02 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 IMX8QM_SCU_GPIO0_02 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IO03 IMX8QM_SCU_GPIO0_03 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON IMX8QM_SCU_GPIO0_03 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 IMX8QM_SCU_GPIO0_03 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IO04 IMX8QM_SCU_GPIO0_04 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON IMX8QM_SCU_GPIO0_04 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define IMX8QM_SCU_GPIO0_04_LSIO_GPIO1_IO00 IMX8QM_SCU_GPIO0_04 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IO05 IMX8QM_SCU_GPIO0_05 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON IMX8QM_SCU_GPIO0_05 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 IMX8QM_SCU_GPIO0_05 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define IMX8QM_SCU_GPIO0_06_SCU_GPIO0_IO06 IMX8QM_SCU_GPIO0_06 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define IMX8QM_SCU_GPIO0_06_SCU_TPM0_CH0 IMX8QM_SCU_GPIO0_06 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 IMX8QM_SCU_GPIO0_06 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define IMX8QM_SCU_GPIO0_07_SCU_GPIO0_IO07 IMX8QM_SCU_GPIO0_07 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define IMX8QM_SCU_GPIO0_07_SCU_TPM0_CH1 IMX8QM_SCU_GPIO0_07 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QM_SCU_GPIO0_07 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define IMX8QM_SCU_GPIO0_07_LSIO_GPIO1_IO03 IMX8QM_SCU_GPIO0_07 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define IMX8QM_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QM_SCU_BOOT_MODE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define IMX8QM_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QM_SCU_BOOT_MODE1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define IMX8QM_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QM_SCU_BOOT_MODE2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define IMX8QM_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QM_SCU_BOOT_MODE3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define IMX8QM_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 IMX8QM_SCU_BOOT_MODE4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define IMX8QM_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL IMX8QM_SCU_BOOT_MODE4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define IMX8QM_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 IMX8QM_SCU_BOOT_MODE5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define IMX8QM_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA IMX8QM_SCU_BOOT_MODE5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define IMX8QM_LVDS0_GPIO00_LVDS0_GPIO0_IO00 IMX8QM_LVDS0_GPIO00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT IMX8QM_LVDS0_GPIO00 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04 IMX8QM_LVDS0_GPIO00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define IMX8QM_LVDS0_GPIO01_LVDS0_GPIO0_IO01 IMX8QM_LVDS0_GPIO01 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 IMX8QM_LVDS0_GPIO01 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define IMX8QM_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL IMX8QM_LVDS0_I2C0_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define IMX8QM_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 IMX8QM_LVDS0_I2C0_SCL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 IMX8QM_LVDS0_I2C0_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define IMX8QM_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA IMX8QM_LVDS0_I2C0_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define IMX8QM_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 IMX8QM_LVDS0_I2C0_SDA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 IMX8QM_LVDS0_I2C0_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL IMX8QM_LVDS0_I2C1_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX IMX8QM_LVDS0_I2C1_SCL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define IMX8QM_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 IMX8QM_LVDS0_I2C1_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA IMX8QM_LVDS0_I2C1_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX IMX8QM_LVDS0_I2C1_SDA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define IMX8QM_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 IMX8QM_LVDS0_I2C1_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define IMX8QM_LVDS1_GPIO00_LVDS1_GPIO0_IO00 IMX8QM_LVDS1_GPIO00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT IMX8QM_LVDS1_GPIO00 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define IMX8QM_LVDS1_GPIO00_LSIO_GPIO1_IO10 IMX8QM_LVDS1_GPIO00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define IMX8QM_LVDS1_GPIO01_LVDS1_GPIO0_IO01 IMX8QM_LVDS1_GPIO01 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 IMX8QM_LVDS1_GPIO01 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define IMX8QM_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL IMX8QM_LVDS1_I2C0_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define IMX8QM_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 IMX8QM_LVDS1_I2C0_SCL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 IMX8QM_LVDS1_I2C0_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define IMX8QM_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA IMX8QM_LVDS1_I2C0_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define IMX8QM_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 IMX8QM_LVDS1_I2C0_SDA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 IMX8QM_LVDS1_I2C0_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL IMX8QM_LVDS1_I2C1_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX IMX8QM_LVDS1_I2C1_SCL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define IMX8QM_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 IMX8QM_LVDS1_I2C1_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA IMX8QM_LVDS1_I2C1_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX IMX8QM_LVDS1_I2C1_SDA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define IMX8QM_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 IMX8QM_LVDS1_I2C1_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QM_MIPI_DSI0_I2C0_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define IMX8QM_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 IMX8QM_MIPI_DSI0_I2C0_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QM_MIPI_DSI0_I2C0_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define IMX8QM_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 IMX8QM_MIPI_DSI0_I2C0_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QM_MIPI_DSI0_GPIO0_00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QM_MIPI_DSI0_GPIO0_00 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define IMX8QM_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 IMX8QM_MIPI_DSI0_GPIO0_00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define IMX8QM_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QM_MIPI_DSI0_GPIO0_01 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 IMX8QM_MIPI_DSI0_GPIO0_01 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QM_MIPI_DSI1_I2C0_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 IMX8QM_MIPI_DSI1_I2C0_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QM_MIPI_DSI1_I2C0_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 IMX8QM_MIPI_DSI1_I2C0_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QM_MIPI_DSI1_GPIO0_00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QM_MIPI_DSI1_GPIO0_00 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 IMX8QM_MIPI_DSI1_GPIO0_00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define IMX8QM_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QM_MIPI_DSI1_GPIO0_01 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 IMX8QM_MIPI_DSI1_GPIO0_01 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QM_MIPI_CSI0_MCLK_OUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 IMX8QM_MIPI_CSI0_MCLK_OUT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QM_MIPI_CSI0_I2C0_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define IMX8QM_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QM_MIPI_CSI0_I2C0_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QM_MIPI_CSI0_I2C0_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define IMX8QM_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QM_MIPI_CSI0_I2C0_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QM_MIPI_CSI0_GPIO0_00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define IMX8QM_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL IMX8QM_MIPI_CSI0_GPIO0_00 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL IMX8QM_MIPI_CSI0_GPIO0_00 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QM_MIPI_CSI0_GPIO0_00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QM_MIPI_CSI0_GPIO0_01 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define IMX8QM_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA IMX8QM_MIPI_CSI0_GPIO0_01 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA IMX8QM_MIPI_CSI0_GPIO0_01 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QM_MIPI_CSI0_GPIO0_01 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT IMX8QM_MIPI_CSI1_MCLK_OUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 IMX8QM_MIPI_CSI1_MCLK_OUT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 IMX8QM_MIPI_CSI1_GPIO0_00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define IMX8QM_MIPI_CSI1_GPIO0_00_DMA_UART4_RX IMX8QM_MIPI_CSI1_GPIO0_00 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 IMX8QM_MIPI_CSI1_GPIO0_00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 IMX8QM_MIPI_CSI1_GPIO0_01 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define IMX8QM_MIPI_CSI1_GPIO0_01_DMA_UART4_TX IMX8QM_MIPI_CSI1_GPIO0_01 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 IMX8QM_MIPI_CSI1_GPIO0_01 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL IMX8QM_MIPI_CSI1_I2C0_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define IMX8QM_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 IMX8QM_MIPI_CSI1_I2C0_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA IMX8QM_MIPI_CSI1_I2C0_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define IMX8QM_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 IMX8QM_MIPI_CSI1_I2C0_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL IMX8QM_HDMI_TX0_TS_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL IMX8QM_HDMI_TX0_TS_SCL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define IMX8QM_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 IMX8QM_HDMI_TX0_TS_SCL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA IMX8QM_HDMI_TX0_TS_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA IMX8QM_HDMI_TX0_TS_SDA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define IMX8QM_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 IMX8QM_HDMI_TX0_TS_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define IMX8QM_ESAI1_FSR_AUD_ESAI1_FSR IMX8QM_ESAI1_FSR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 IMX8QM_ESAI1_FSR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define IMX8QM_ESAI1_FST_AUD_ESAI1_FST IMX8QM_ESAI1_FST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define IMX8QM_ESAI1_FST_AUD_SPDIF0_EXT_CLK IMX8QM_ESAI1_FST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 IMX8QM_ESAI1_FST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define IMX8QM_ESAI1_SCKR_AUD_ESAI1_SCKR IMX8QM_ESAI1_SCKR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 IMX8QM_ESAI1_SCKR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define IMX8QM_ESAI1_SCKT_AUD_ESAI1_SCKT IMX8QM_ESAI1_SCKT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define IMX8QM_ESAI1_SCKT_AUD_SAI2_RXC IMX8QM_ESAI1_SCKT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define IMX8QM_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK IMX8QM_ESAI1_SCKT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 IMX8QM_ESAI1_SCKT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define IMX8QM_ESAI1_TX0_AUD_ESAI1_TX0 IMX8QM_ESAI1_TX0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define IMX8QM_ESAI1_TX0_AUD_SAI2_RXD IMX8QM_ESAI1_TX0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define IMX8QM_ESAI1_TX0_AUD_SPDIF0_RX IMX8QM_ESAI1_TX0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 IMX8QM_ESAI1_TX0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define IMX8QM_ESAI1_TX1_AUD_ESAI1_TX1 IMX8QM_ESAI1_TX1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define IMX8QM_ESAI1_TX1_AUD_SAI2_RXFS IMX8QM_ESAI1_TX1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define IMX8QM_ESAI1_TX1_AUD_SPDIF0_TX IMX8QM_ESAI1_TX1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 IMX8QM_ESAI1_TX1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define IMX8QM_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 IMX8QM_ESAI1_TX2_RX3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define IMX8QM_ESAI1_TX2_RX3_AUD_SPDIF0_RX IMX8QM_ESAI1_TX2_RX3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define IMX8QM_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 IMX8QM_ESAI1_TX2_RX3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define IMX8QM_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 IMX8QM_ESAI1_TX3_RX2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define IMX8QM_ESAI1_TX3_RX2_AUD_SPDIF0_TX IMX8QM_ESAI1_TX3_RX2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 IMX8QM_ESAI1_TX3_RX2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define IMX8QM_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 IMX8QM_ESAI1_TX4_RX1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define IMX8QM_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 IMX8QM_ESAI1_TX4_RX1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define IMX8QM_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 IMX8QM_ESAI1_TX5_RX0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 IMX8QM_ESAI1_TX5_RX0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX IMX8QM_SPDIF0_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define IMX8QM_SPDIF0_RX_AUD_MQS_R IMX8QM_SPDIF0_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define IMX8QM_SPDIF0_RX_AUD_ACM_MCLK_IN1 IMX8QM_SPDIF0_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define IMX8QM_SPDIF0_RX_LSIO_GPIO2_IO14 IMX8QM_SPDIF0_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX IMX8QM_SPDIF0_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define IMX8QM_SPDIF0_TX_AUD_MQS_L IMX8QM_SPDIF0_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define IMX8QM_SPDIF0_TX_AUD_ACM_MCLK_OUT1 IMX8QM_SPDIF0_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 IMX8QM_SPDIF0_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define IMX8QM_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK IMX8QM_SPDIF0_EXT_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define IMX8QM_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 IMX8QM_SPDIF0_EXT_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 IMX8QM_SPDIF0_EXT_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define IMX8QM_SPI3_SCK_DMA_SPI3_SCK IMX8QM_SPI3_SCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 IMX8QM_SPI3_SCK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define IMX8QM_SPI3_SDO_DMA_SPI3_SDO IMX8QM_SPI3_SDO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define IMX8QM_SPI3_SDO_DMA_FTM_CH0 IMX8QM_SPI3_SDO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18 IMX8QM_SPI3_SDO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define IMX8QM_SPI3_SDI_DMA_SPI3_SDI IMX8QM_SPI3_SDI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define IMX8QM_SPI3_SDI_DMA_FTM_CH1 IMX8QM_SPI3_SDI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19 IMX8QM_SPI3_SDI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define IMX8QM_SPI3_CS0_DMA_SPI3_CS0 IMX8QM_SPI3_CS0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define IMX8QM_SPI3_CS0_DMA_FTM_CH2 IMX8QM_SPI3_CS0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 IMX8QM_SPI3_CS0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define IMX8QM_SPI3_CS1_DMA_SPI3_CS1 IMX8QM_SPI3_CS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 IMX8QM_SPI3_CS1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR IMX8QM_ESAI0_FSR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 IMX8QM_ESAI0_FSR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define IMX8QM_ESAI0_FST_AUD_ESAI0_FST IMX8QM_ESAI0_FST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 IMX8QM_ESAI0_FST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR IMX8QM_ESAI0_SCKR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24 IMX8QM_ESAI0_SCKR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT IMX8QM_ESAI0_SCKT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25 IMX8QM_ESAI0_SCKT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 IMX8QM_ESAI0_TX0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26 IMX8QM_ESAI0_TX0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 IMX8QM_ESAI0_TX1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27 IMX8QM_ESAI0_TX1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 IMX8QM_ESAI0_TX2_RX3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 IMX8QM_ESAI0_TX2_RX3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 IMX8QM_ESAI0_TX3_RX2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 IMX8QM_ESAI0_TX3_RX2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 IMX8QM_ESAI0_TX4_RX1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 IMX8QM_ESAI0_TX4_RX1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 IMX8QM_ESAI0_TX5_RX0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 IMX8QM_ESAI0_TX5_RX0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define IMX8QM_MCLK_IN0_AUD_ACM_MCLK_IN0 IMX8QM_MCLK_IN0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define IMX8QM_MCLK_IN0_AUD_ESAI0_RX_HF_CLK IMX8QM_MCLK_IN0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define IMX8QM_MCLK_IN0_AUD_ESAI1_RX_HF_CLK IMX8QM_MCLK_IN0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00 IMX8QM_MCLK_IN0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 IMX8QM_MCLK_OUT0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define IMX8QM_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK IMX8QM_MCLK_OUT0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define IMX8QM_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK IMX8QM_MCLK_OUT0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define IMX8QM_MCLK_OUT0_LSIO_GPIO3_IO01 IMX8QM_MCLK_OUT0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define IMX8QM_SPI0_SCK_DMA_SPI0_SCK IMX8QM_SPI0_SCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define IMX8QM_SPI0_SCK_AUD_SAI0_RXC IMX8QM_SPI0_SCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define IMX8QM_SPI0_SCK_LSIO_GPIO3_IO02 IMX8QM_SPI0_SCK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define IMX8QM_SPI0_SDO_DMA_SPI0_SDO IMX8QM_SPI0_SDO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define IMX8QM_SPI0_SDO_AUD_SAI0_TXD IMX8QM_SPI0_SDO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define IMX8QM_SPI0_SDO_LSIO_GPIO3_IO03 IMX8QM_SPI0_SDO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define IMX8QM_SPI0_SDI_DMA_SPI0_SDI IMX8QM_SPI0_SDI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define IMX8QM_SPI0_SDI_AUD_SAI0_RXD IMX8QM_SPI0_SDI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define IMX8QM_SPI0_SDI_LSIO_GPIO3_IO04 IMX8QM_SPI0_SDI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define IMX8QM_SPI0_CS0_DMA_SPI0_CS0 IMX8QM_SPI0_CS0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define IMX8QM_SPI0_CS0_AUD_SAI0_RXFS IMX8QM_SPI0_CS0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 IMX8QM_SPI0_CS0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define IMX8QM_SPI0_CS1_DMA_SPI0_CS1 IMX8QM_SPI0_CS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define IMX8QM_SPI0_CS1_AUD_SAI0_TXC IMX8QM_SPI0_CS1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 IMX8QM_SPI0_CS1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define IMX8QM_SPI2_SCK_DMA_SPI2_SCK IMX8QM_SPI2_SCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define IMX8QM_SPI2_SCK_LSIO_GPIO3_IO07 IMX8QM_SPI2_SCK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define IMX8QM_SPI2_SDO_DMA_SPI2_SDO IMX8QM_SPI2_SDO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define IMX8QM_SPI2_SDO_LSIO_GPIO3_IO08 IMX8QM_SPI2_SDO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define IMX8QM_SPI2_SDI_DMA_SPI2_SDI IMX8QM_SPI2_SDI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define IMX8QM_SPI2_SDI_LSIO_GPIO3_IO09 IMX8QM_SPI2_SDI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define IMX8QM_SPI2_CS0_DMA_SPI2_CS0 IMX8QM_SPI2_CS0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 IMX8QM_SPI2_CS0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define IMX8QM_SPI2_CS1_DMA_SPI2_CS1 IMX8QM_SPI2_CS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define IMX8QM_SPI2_CS1_AUD_SAI0_TXFS IMX8QM_SPI2_CS1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 IMX8QM_SPI2_CS1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define IMX8QM_SAI1_RXC_AUD_SAI1_RXC IMX8QM_SAI1_RXC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define IMX8QM_SAI1_RXC_AUD_SAI0_TXD IMX8QM_SAI1_RXC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12 IMX8QM_SAI1_RXC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define IMX8QM_SAI1_RXD_AUD_SAI1_RXD IMX8QM_SAI1_RXD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define IMX8QM_SAI1_RXD_AUD_SAI0_TXFS IMX8QM_SAI1_RXD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define IMX8QM_SAI1_RXD_LSIO_GPIO3_IO13 IMX8QM_SAI1_RXD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS IMX8QM_SAI1_RXFS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define IMX8QM_SAI1_RXFS_AUD_SAI0_RXD IMX8QM_SAI1_RXFS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14 IMX8QM_SAI1_RXFS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define IMX8QM_SAI1_TXC_AUD_SAI1_TXC IMX8QM_SAI1_TXC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define IMX8QM_SAI1_TXC_AUD_SAI0_TXC IMX8QM_SAI1_TXC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define IMX8QM_SAI1_TXC_LSIO_GPIO3_IO15 IMX8QM_SAI1_TXC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define IMX8QM_SAI1_TXD_AUD_SAI1_TXD IMX8QM_SAI1_TXD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define IMX8QM_SAI1_TXD_AUD_SAI1_RXC IMX8QM_SAI1_TXD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define IMX8QM_SAI1_TXD_LSIO_GPIO3_IO16 IMX8QM_SAI1_TXD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS IMX8QM_SAI1_TXFS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define IMX8QM_SAI1_TXFS_AUD_SAI1_RXFS IMX8QM_SAI1_TXFS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define IMX8QM_SAI1_TXFS_LSIO_GPIO3_IO17 IMX8QM_SAI1_TXFS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define IMX8QM_ADC_IN7_DMA_ADC1_IN3 IMX8QM_ADC_IN7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define IMX8QM_ADC_IN7_DMA_SPI1_CS1 IMX8QM_ADC_IN7 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define IMX8QM_ADC_IN7_LSIO_KPP0_ROW3 IMX8QM_ADC_IN7 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 IMX8QM_ADC_IN7 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define IMX8QM_ADC_IN6_DMA_ADC1_IN2 IMX8QM_ADC_IN6 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define IMX8QM_ADC_IN6_DMA_SPI1_CS0 IMX8QM_ADC_IN6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define IMX8QM_ADC_IN6_LSIO_KPP0_ROW2 IMX8QM_ADC_IN6 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 IMX8QM_ADC_IN6 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define IMX8QM_ADC_IN5_DMA_ADC1_IN1 IMX8QM_ADC_IN5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define IMX8QM_ADC_IN5_DMA_SPI1_SDI IMX8QM_ADC_IN5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define IMX8QM_ADC_IN5_LSIO_KPP0_ROW1 IMX8QM_ADC_IN5 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define IMX8QM_ADC_IN5_LSIO_GPIO3_IO23 IMX8QM_ADC_IN5 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define IMX8QM_ADC_IN4_DMA_ADC1_IN0 IMX8QM_ADC_IN4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define IMX8QM_ADC_IN4_DMA_SPI1_SDO IMX8QM_ADC_IN4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define IMX8QM_ADC_IN4_LSIO_KPP0_ROW0 IMX8QM_ADC_IN4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define IMX8QM_ADC_IN4_LSIO_GPIO3_IO22 IMX8QM_ADC_IN4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define IMX8QM_ADC_IN3_DMA_ADC0_IN3 IMX8QM_ADC_IN3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define IMX8QM_ADC_IN3_DMA_SPI1_SCK IMX8QM_ADC_IN3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define IMX8QM_ADC_IN3_LSIO_KPP0_COL3 IMX8QM_ADC_IN3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define IMX8QM_ADC_IN3_LSIO_GPIO3_IO21 IMX8QM_ADC_IN3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define IMX8QM_ADC_IN2_DMA_ADC0_IN2 IMX8QM_ADC_IN2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define IMX8QM_ADC_IN2_LSIO_KPP0_COL2 IMX8QM_ADC_IN2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 IMX8QM_ADC_IN2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define IMX8QM_ADC_IN1_DMA_ADC0_IN1 IMX8QM_ADC_IN1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define IMX8QM_ADC_IN1_LSIO_KPP0_COL1 IMX8QM_ADC_IN1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define IMX8QM_ADC_IN1_LSIO_GPIO3_IO19 IMX8QM_ADC_IN1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define IMX8QM_ADC_IN0_DMA_ADC0_IN0 IMX8QM_ADC_IN0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define IMX8QM_ADC_IN0_LSIO_KPP0_COL0 IMX8QM_ADC_IN0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define IMX8QM_ADC_IN0_LSIO_GPIO3_IO18 IMX8QM_ADC_IN0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define IMX8QM_MLB_SIG_CONN_MLB_SIG IMX8QM_MLB_SIG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define IMX8QM_MLB_SIG_AUD_SAI3_RXC IMX8QM_MLB_SIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define IMX8QM_MLB_SIG_LSIO_GPIO3_IO26 IMX8QM_MLB_SIG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define IMX8QM_MLB_CLK_CONN_MLB_CLK IMX8QM_MLB_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define IMX8QM_MLB_CLK_AUD_SAI3_RXFS IMX8QM_MLB_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define IMX8QM_MLB_CLK_LSIO_GPIO3_IO27 IMX8QM_MLB_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define IMX8QM_MLB_DATA_CONN_MLB_DATA IMX8QM_MLB_DATA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define IMX8QM_MLB_DATA_AUD_SAI3_RXD IMX8QM_MLB_DATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define IMX8QM_MLB_DATA_LSIO_GPIO3_IO28 IMX8QM_MLB_DATA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX IMX8QM_FLEXCAN0_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define IMX8QM_FLEXCAN0_RX_LSIO_GPIO3_IO29 IMX8QM_FLEXCAN0_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX IMX8QM_FLEXCAN0_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define IMX8QM_FLEXCAN0_TX_LSIO_GPIO3_IO30 IMX8QM_FLEXCAN0_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX IMX8QM_FLEXCAN1_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define IMX8QM_FLEXCAN1_RX_LSIO_GPIO3_IO31 IMX8QM_FLEXCAN1_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX IMX8QM_FLEXCAN1_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define IMX8QM_FLEXCAN1_TX_LSIO_GPIO4_IO00 IMX8QM_FLEXCAN1_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX IMX8QM_FLEXCAN2_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01 IMX8QM_FLEXCAN2_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX IMX8QM_FLEXCAN2_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02 IMX8QM_FLEXCAN2_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define IMX8QM_USB_SS3_TC0_DMA_I2C1_SCL IMX8QM_USB_SS3_TC0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QM_USB_SS3_TC0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QM_USB_SS3_TC0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL IMX8QM_USB_SS3_TC1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define IMX8QM_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QM_USB_SS3_TC1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QM_USB_SS3_TC1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define IMX8QM_USB_SS3_TC2_DMA_I2C1_SDA IMX8QM_USB_SS3_TC2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QM_USB_SS3_TC2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define IMX8QM_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QM_USB_SS3_TC2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA IMX8QM_USB_SS3_TC3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define IMX8QM_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QM_USB_SS3_TC3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QM_USB_SS3_TC3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define IMX8QM_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QM_USDHC1_RESET_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 IMX8QM_USDHC1_RESET_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QM_USDHC1_VSELECT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define IMX8QM_USDHC1_VSELECT_LSIO_GPIO4_IO08 IMX8QM_USDHC1_VSELECT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define IMX8QM_USDHC2_RESET_B_CONN_USDHC2_RESET_B IMX8QM_USDHC2_RESET_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 IMX8QM_USDHC2_RESET_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT IMX8QM_USDHC2_VSELECT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 IMX8QM_USDHC2_VSELECT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define IMX8QM_USDHC2_WP_CONN_USDHC2_WP IMX8QM_USDHC2_WP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 IMX8QM_USDHC2_WP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define IMX8QM_USDHC2_CD_B_CONN_USDHC2_CD_B IMX8QM_USDHC2_CD_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 IMX8QM_USDHC2_CD_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO IMX8QM_ENET0_MDIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define IMX8QM_ENET0_MDIO_DMA_I2C4_SDA IMX8QM_ENET0_MDIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 IMX8QM_ENET0_MDIO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define IMX8QM_ENET0_MDC_CONN_ENET0_MDC IMX8QM_ENET0_MDC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define IMX8QM_ENET0_MDC_DMA_I2C4_SCL IMX8QM_ENET0_MDC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 IMX8QM_ENET0_MDC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QM_ENET0_REFCLK_125M_25M 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QM_ENET0_REFCLK_125M_25M 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 IMX8QM_ENET0_REFCLK_125M_25M 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M IMX8QM_ENET1_REFCLK_125M_25M 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QM_ENET1_REFCLK_125M_25M 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 IMX8QM_ENET1_REFCLK_125M_25M 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO IMX8QM_ENET1_MDIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define IMX8QM_ENET1_MDIO_DMA_I2C4_SDA IMX8QM_ENET1_MDIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17 IMX8QM_ENET1_MDIO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define IMX8QM_ENET1_MDC_CONN_ENET1_MDC IMX8QM_ENET1_MDC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define IMX8QM_ENET1_MDC_DMA_I2C4_SCL IMX8QM_ENET1_MDC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18 IMX8QM_ENET1_MDC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define IMX8QM_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B IMX8QM_QSPI1A_SS0_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 IMX8QM_QSPI1A_SS0_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B IMX8QM_QSPI1A_SS1_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 IMX8QM_QSPI1A_SS1_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20 IMX8QM_QSPI1A_SS1_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define IMX8QM_QSPI1A_SCLK_LSIO_QSPI1A_SCLK IMX8QM_QSPI1A_SCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21 IMX8QM_QSPI1A_SCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define IMX8QM_QSPI1A_DQS_LSIO_QSPI1A_DQS IMX8QM_QSPI1A_DQS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 IMX8QM_QSPI1A_DQS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define IMX8QM_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 IMX8QM_QSPI1A_DATA3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define IMX8QM_QSPI1A_DATA3_DMA_I2C1_SDA IMX8QM_QSPI1A_DATA3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define IMX8QM_QSPI1A_DATA3_CONN_USB_OTG1_OC IMX8QM_QSPI1A_DATA3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23 IMX8QM_QSPI1A_DATA3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define IMX8QM_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 IMX8QM_QSPI1A_DATA2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define IMX8QM_QSPI1A_DATA2_DMA_I2C1_SCL IMX8QM_QSPI1A_DATA2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define IMX8QM_QSPI1A_DATA2_CONN_USB_OTG2_PWR IMX8QM_QSPI1A_DATA2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24 IMX8QM_QSPI1A_DATA2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define IMX8QM_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 IMX8QM_QSPI1A_DATA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define IMX8QM_QSPI1A_DATA1_DMA_I2C1_SDA IMX8QM_QSPI1A_DATA1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define IMX8QM_QSPI1A_DATA1_CONN_USB_OTG2_OC IMX8QM_QSPI1A_DATA1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 IMX8QM_QSPI1A_DATA1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define IMX8QM_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 IMX8QM_QSPI1A_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 IMX8QM_QSPI1A_DATA0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QM_QSPI0A_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QM_QSPI0A_DATA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QM_QSPI0A_DATA2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QM_QSPI0A_DATA3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QM_QSPI0A_DQS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QM_QSPI0A_SS0_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QM_QSPI0A_SS1_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 IMX8QM_QSPI0A_SS1_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QM_QSPI0A_SCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QM_QSPI0B_SCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QM_QSPI0B_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QM_QSPI0B_DATA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QM_QSPI0B_DATA2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QM_QSPI0B_DATA3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QM_QSPI0B_DQS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QM_QSPI0B_SS0_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QM_QSPI0B_SS1_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 IMX8QM_QSPI0B_SS1_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define IMX8QM_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QM_PCIE_CTRL0_CLKREQ_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 IMX8QM_PCIE_CTRL0_CLKREQ_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define IMX8QM_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QM_PCIE_CTRL0_WAKE_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 IMX8QM_PCIE_CTRL0_WAKE_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define IMX8QM_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QM_PCIE_CTRL0_PERST_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 IMX8QM_PCIE_CTRL0_PERST_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B IMX8QM_PCIE_CTRL1_CLKREQ_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define IMX8QM_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA IMX8QM_PCIE_CTRL1_CLKREQ_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define IMX8QM_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC IMX8QM_PCIE_CTRL1_CLKREQ_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 IMX8QM_PCIE_CTRL1_CLKREQ_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define IMX8QM_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B IMX8QM_PCIE_CTRL1_WAKE_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define IMX8QM_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL IMX8QM_PCIE_CTRL1_WAKE_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define IMX8QM_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR IMX8QM_PCIE_CTRL1_WAKE_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 IMX8QM_PCIE_CTRL1_WAKE_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define IMX8QM_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B IMX8QM_PCIE_CTRL1_PERST_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define IMX8QM_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL IMX8QM_PCIE_CTRL1_PERST_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define IMX8QM_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR IMX8QM_PCIE_CTRL1_PERST_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 IMX8QM_PCIE_CTRL1_PERST_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA IMX8QM_USB_HSIC0_DATA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define IMX8QM_USB_HSIC0_DATA_DMA_I2C1_SDA IMX8QM_USB_HSIC0_DATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define IMX8QM_USB_HSIC0_DATA_LSIO_GPIO5_IO01 IMX8QM_USB_HSIC0_DATA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE IMX8QM_USB_HSIC0_STROBE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define IMX8QM_USB_HSIC0_STROBE_DMA_I2C1_SCL IMX8QM_USB_HSIC0_STROBE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define IMX8QM_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 IMX8QM_USB_HSIC0_STROBE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK IMX8QM_EMMC0_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define IMX8QM_EMMC0_CLK_CONN_NAND_READY_B IMX8QM_EMMC0_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD IMX8QM_EMMC0_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define IMX8QM_EMMC0_CMD_CONN_NAND_DQS IMX8QM_EMMC0_CMD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define IMX8QM_EMMC0_CMD_AUD_MQS_R IMX8QM_EMMC0_CMD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define IMX8QM_EMMC0_CMD_LSIO_GPIO5_IO03 IMX8QM_EMMC0_CMD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QM_EMMC0_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define IMX8QM_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QM_EMMC0_DATA0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define IMX8QM_EMMC0_DATA0_LSIO_GPIO5_IO04 IMX8QM_EMMC0_DATA0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QM_EMMC0_DATA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define IMX8QM_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QM_EMMC0_DATA1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define IMX8QM_EMMC0_DATA1_LSIO_GPIO5_IO05 IMX8QM_EMMC0_DATA1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QM_EMMC0_DATA2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define IMX8QM_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QM_EMMC0_DATA2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define IMX8QM_EMMC0_DATA2_LSIO_GPIO5_IO06 IMX8QM_EMMC0_DATA2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QM_EMMC0_DATA3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define IMX8QM_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QM_EMMC0_DATA3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define IMX8QM_EMMC0_DATA3_LSIO_GPIO5_IO07 IMX8QM_EMMC0_DATA3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QM_EMMC0_DATA4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define IMX8QM_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QM_EMMC0_DATA4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define IMX8QM_EMMC0_DATA4_LSIO_GPIO5_IO08 IMX8QM_EMMC0_DATA4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QM_EMMC0_DATA5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define IMX8QM_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QM_EMMC0_DATA5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define IMX8QM_EMMC0_DATA5_LSIO_GPIO5_IO09 IMX8QM_EMMC0_DATA5 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QM_EMMC0_DATA6 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define IMX8QM_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QM_EMMC0_DATA6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define IMX8QM_EMMC0_DATA6_LSIO_GPIO5_IO10 IMX8QM_EMMC0_DATA6 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QM_EMMC0_DATA7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define IMX8QM_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QM_EMMC0_DATA7 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define IMX8QM_EMMC0_DATA7_LSIO_GPIO5_IO11 IMX8QM_EMMC0_DATA7 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QM_EMMC0_STROBE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define IMX8QM_EMMC0_STROBE_CONN_NAND_CLE IMX8QM_EMMC0_STROBE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define IMX8QM_EMMC0_STROBE_LSIO_GPIO5_IO12 IMX8QM_EMMC0_STROBE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QM_EMMC0_RESET_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define IMX8QM_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QM_EMMC0_RESET_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define IMX8QM_EMMC0_RESET_B_CONN_USDHC1_VSELECT IMX8QM_EMMC0_RESET_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define IMX8QM_EMMC0_RESET_B_LSIO_GPIO5_IO13 IMX8QM_EMMC0_RESET_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK IMX8QM_USDHC1_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define IMX8QM_USDHC1_CLK_AUD_MQS_R IMX8QM_USDHC1_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD IMX8QM_USDHC1_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define IMX8QM_USDHC1_CMD_AUD_MQS_L IMX8QM_USDHC1_CMD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define IMX8QM_USDHC1_CMD_LSIO_GPIO5_IO14 IMX8QM_USDHC1_CMD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QM_USDHC1_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define IMX8QM_USDHC1_DATA0_CONN_NAND_RE_N IMX8QM_USDHC1_DATA0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define IMX8QM_USDHC1_DATA0_LSIO_GPIO5_IO15 IMX8QM_USDHC1_DATA0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QM_USDHC1_DATA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define IMX8QM_USDHC1_DATA1_CONN_NAND_RE_P IMX8QM_USDHC1_DATA1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define IMX8QM_USDHC1_DATA1_LSIO_GPIO5_IO16 IMX8QM_USDHC1_DATA1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QM_USDHC1_DATA2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define IMX8QM_USDHC1_DATA2_CONN_NAND_DQS_N IMX8QM_USDHC1_DATA2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define IMX8QM_USDHC1_DATA2_LSIO_GPIO5_IO17 IMX8QM_USDHC1_DATA2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QM_USDHC1_DATA3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define IMX8QM_USDHC1_DATA3_CONN_NAND_DQS_P IMX8QM_USDHC1_DATA3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define IMX8QM_USDHC1_DATA3_LSIO_GPIO5_IO18 IMX8QM_USDHC1_DATA3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 IMX8QM_USDHC1_DATA4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define IMX8QM_USDHC1_DATA4_CONN_NAND_CE0_B IMX8QM_USDHC1_DATA4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define IMX8QM_USDHC1_DATA4_AUD_MQS_R IMX8QM_USDHC1_DATA4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 IMX8QM_USDHC1_DATA4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 IMX8QM_USDHC1_DATA5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define IMX8QM_USDHC1_DATA5_CONN_NAND_RE_B IMX8QM_USDHC1_DATA5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define IMX8QM_USDHC1_DATA5_AUD_MQS_L IMX8QM_USDHC1_DATA5 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 IMX8QM_USDHC1_DATA5 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 IMX8QM_USDHC1_DATA6 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define IMX8QM_USDHC1_DATA6_CONN_NAND_WE_B IMX8QM_USDHC1_DATA6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define IMX8QM_USDHC1_DATA6_CONN_USDHC1_WP IMX8QM_USDHC1_DATA6 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 IMX8QM_USDHC1_DATA6 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 IMX8QM_USDHC1_DATA7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define IMX8QM_USDHC1_DATA7_CONN_NAND_ALE IMX8QM_USDHC1_DATA7 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define IMX8QM_USDHC1_DATA7_CONN_USDHC1_CD_B IMX8QM_USDHC1_DATA7 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 IMX8QM_USDHC1_DATA7 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define IMX8QM_USDHC1_STROBE_CONN_USDHC1_STROBE IMX8QM_USDHC1_STROBE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define IMX8QM_USDHC1_STROBE_CONN_NAND_CE1_B IMX8QM_USDHC1_STROBE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define IMX8QM_USDHC1_STROBE_CONN_USDHC1_RESET_B IMX8QM_USDHC1_STROBE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 IMX8QM_USDHC1_STROBE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK IMX8QM_USDHC2_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define IMX8QM_USDHC2_CLK_AUD_MQS_R IMX8QM_USDHC2_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define IMX8QM_USDHC2_CLK_LSIO_GPIO5_IO24 IMX8QM_USDHC2_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD IMX8QM_USDHC2_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define IMX8QM_USDHC2_CMD_AUD_MQS_L IMX8QM_USDHC2_CMD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 IMX8QM_USDHC2_CMD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 IMX8QM_USDHC2_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define IMX8QM_USDHC2_DATA0_DMA_UART4_RX IMX8QM_USDHC2_DATA0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define IMX8QM_USDHC2_DATA0_LSIO_GPIO5_IO26 IMX8QM_USDHC2_DATA0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 IMX8QM_USDHC2_DATA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define IMX8QM_USDHC2_DATA1_DMA_UART4_TX IMX8QM_USDHC2_DATA1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 IMX8QM_USDHC2_DATA1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 IMX8QM_USDHC2_DATA2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define IMX8QM_USDHC2_DATA2_DMA_UART4_CTS_B IMX8QM_USDHC2_DATA2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define IMX8QM_USDHC2_DATA2_LSIO_GPIO5_IO28 IMX8QM_USDHC2_DATA2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 IMX8QM_USDHC2_DATA3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define IMX8QM_USDHC2_DATA3_DMA_UART4_RTS_B IMX8QM_USDHC2_DATA3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 IMX8QM_USDHC2_DATA3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QM_ENET0_RGMII_TXC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QM_ENET0_RGMII_TXC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QM_ENET0_RGMII_TXC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 IMX8QM_ENET0_RGMII_TXC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QM_ENET0_RGMII_TX_CTL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 IMX8QM_ENET0_RGMII_TX_CTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QM_ENET0_RGMII_TXD0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 IMX8QM_ENET0_RGMII_TXD0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QM_ENET0_RGMII_TXD1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 IMX8QM_ENET0_RGMII_TXD1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QM_ENET0_RGMII_TXD2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define IMX8QM_ENET0_RGMII_TXD2_DMA_UART3_TX IMX8QM_ENET0_RGMII_TXD2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define IMX8QM_ENET0_RGMII_TXD2_VPU_TSI_S1_VID IMX8QM_ENET0_RGMII_TXD2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 IMX8QM_ENET0_RGMII_TXD2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QM_ENET0_RGMII_TXD3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define IMX8QM_ENET0_RGMII_TXD3_DMA_UART3_RTS_B IMX8QM_ENET0_RGMII_TXD3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define IMX8QM_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC IMX8QM_ENET0_RGMII_TXD3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 IMX8QM_ENET0_RGMII_TXD3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QM_ENET0_RGMII_RXC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define IMX8QM_ENET0_RGMII_RXC_DMA_UART3_CTS_B IMX8QM_ENET0_RGMII_RXC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define IMX8QM_ENET0_RGMII_RXC_VPU_TSI_S1_DATA IMX8QM_ENET0_RGMII_RXC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 IMX8QM_ENET0_RGMII_RXC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QM_ENET0_RGMII_RX_CTL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define IMX8QM_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID IMX8QM_ENET0_RGMII_RX_CTL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8QM_ENET0_RGMII_RX_CTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QM_ENET0_RGMII_RXD0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define IMX8QM_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC IMX8QM_ENET0_RGMII_RXD0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 IMX8QM_ENET0_RGMII_RXD0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QM_ENET0_RGMII_RXD1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define IMX8QM_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA IMX8QM_ENET0_RGMII_RXD1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 IMX8QM_ENET0_RGMII_RXD1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QM_ENET0_RGMII_RXD2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QM_ENET0_RGMII_RXD2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define IMX8QM_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK IMX8QM_ENET0_RGMII_RXD2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 IMX8QM_ENET0_RGMII_RXD2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QM_ENET0_RGMII_RXD3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define IMX8QM_ENET0_RGMII_RXD3_DMA_UART3_RX IMX8QM_ENET0_RGMII_RXD3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define IMX8QM_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK IMX8QM_ENET0_RGMII_RXD3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 IMX8QM_ENET0_RGMII_RXD3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC IMX8QM_ENET1_RGMII_TXC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT IMX8QM_ENET1_RGMII_TXC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN IMX8QM_ENET1_RGMII_TXC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 IMX8QM_ENET1_RGMII_TXC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL IMX8QM_ENET1_RGMII_TX_CTL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 IMX8QM_ENET1_RGMII_TX_CTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 IMX8QM_ENET1_RGMII_TXD0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 IMX8QM_ENET1_RGMII_TXD0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 IMX8QM_ENET1_RGMII_TXD1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 IMX8QM_ENET1_RGMII_TXD1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 IMX8QM_ENET1_RGMII_TXD2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define IMX8QM_ENET1_RGMII_TXD2_DMA_UART3_TX IMX8QM_ENET1_RGMII_TXD2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define IMX8QM_ENET1_RGMII_TXD2_VPU_TSI_S1_VID IMX8QM_ENET1_RGMII_TXD2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 IMX8QM_ENET1_RGMII_TXD2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 IMX8QM_ENET1_RGMII_TXD3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B IMX8QM_ENET1_RGMII_TXD3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define IMX8QM_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC IMX8QM_ENET1_RGMII_TXD3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define IMX8QM_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 IMX8QM_ENET1_RGMII_TXD3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC IMX8QM_ENET1_RGMII_RXC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B IMX8QM_ENET1_RGMII_RXC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define IMX8QM_ENET1_RGMII_RXC_VPU_TSI_S1_DATA IMX8QM_ENET1_RGMII_RXC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define IMX8QM_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 IMX8QM_ENET1_RGMII_RXC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL IMX8QM_ENET1_RGMII_RX_CTL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define IMX8QM_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID IMX8QM_ENET1_RGMII_RX_CTL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 IMX8QM_ENET1_RGMII_RX_CTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 IMX8QM_ENET1_RGMII_RXD0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define IMX8QM_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC IMX8QM_ENET1_RGMII_RXD0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 IMX8QM_ENET1_RGMII_RXD0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 IMX8QM_ENET1_RGMII_RXD1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define IMX8QM_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA IMX8QM_ENET1_RGMII_RXD1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 IMX8QM_ENET1_RGMII_RXD1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 IMX8QM_ENET1_RGMII_RXD2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER IMX8QM_ENET1_RGMII_RXD2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define IMX8QM_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK IMX8QM_ENET1_RGMII_RXD2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 IMX8QM_ENET1_RGMII_RXD2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 IMX8QM_ENET1_RGMII_RXD3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define IMX8QM_ENET1_RGMII_RXD3_DMA_UART3_RX IMX8QM_ENET1_RGMII_RXD3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define IMX8QM_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK IMX8QM_ENET1_RGMII_RXD3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 IMX8QM_ENET1_RGMII_RXD3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #endif /* _IMX8QM_PADS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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