^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2019~2020 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _IMX8DXL_PADS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _IMX8DXL_PADS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* pin id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IMX8DXL_PCIE_CTRL0_PERST_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX8DXL_PCIE_CTRL0_CLKREQ_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX8DXL_PCIE_CTRL0_WAKE_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX8DXL_USB_SS3_TC0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX8DXL_USB_SS3_TC1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX8DXL_USB_SS3_TC2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX8DXL_USB_SS3_TC3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX8DXL_EMMC0_CLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX8DXL_EMMC0_CMD 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX8DXL_EMMC0_DATA0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX8DXL_EMMC0_DATA1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX8DXL_EMMC0_DATA2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX8DXL_EMMC0_DATA3 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX8DXL_EMMC0_DATA4 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX8DXL_EMMC0_DATA5 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX8DXL_EMMC0_DATA6 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX8DXL_EMMC0_DATA7 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX8DXL_EMMC0_STROBE 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX8DXL_EMMC0_RESET_B 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX8DXL_USDHC1_RESET_B 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX8DXL_USDHC1_VSELECT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX8DXL_CTL_NAND_RE_P_N 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX8DXL_USDHC1_WP 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX8DXL_USDHC1_CD_B 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX8DXL_CTL_NAND_DQS_P_N 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX8DXL_ENET0_RGMII_TXC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX8DXL_ENET0_RGMII_TX_CTL 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX8DXL_ENET0_RGMII_TXD0 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX8DXL_ENET0_RGMII_TXD1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX8DXL_ENET0_RGMII_TXD2 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX8DXL_ENET0_RGMII_TXD3 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX8DXL_ENET0_RGMII_RXC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX8DXL_ENET0_RGMII_RX_CTL 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX8DXL_ENET0_RGMII_RXD0 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX8DXL_ENET0_RGMII_RXD1 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX8DXL_ENET0_RGMII_RXD2 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX8DXL_ENET0_RGMII_RXD3 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX8DXL_ENET0_REFCLK_125M_25M 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX8DXL_ENET0_MDIO 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX8DXL_ENET0_MDC 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX8DXL_ENET1_RGMII_TXC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX8DXL_ENET1_RGMII_TXD2 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX8DXL_ENET1_RGMII_TX_CTL 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX8DXL_ENET1_RGMII_TXD3 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX8DXL_ENET1_RGMII_RXC 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX8DXL_ENET1_RGMII_RXD3 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX8DXL_ENET1_RGMII_RXD2 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX8DXL_ENET1_RGMII_RXD1 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX8DXL_ENET1_RGMII_TXD0 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX8DXL_ENET1_RGMII_TXD1 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX8DXL_ENET1_RGMII_RXD0 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX8DXL_ENET1_RGMII_RX_CTL 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX8DXL_ENET1_REFCLK_125M_25M 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX8DXL_SPI3_SCK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX8DXL_SPI3_SDO 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX8DXL_SPI3_SDI 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX8DXL_SPI3_CS0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX8DXL_SPI3_CS1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX8DXL_MCLK_IN1 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX8DXL_MCLK_IN0 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX8DXL_MCLK_OUT0 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX8DXL_UART1_TX 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX8DXL_UART1_RX 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX8DXL_UART1_RTS_B 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX8DXL_UART1_CTS_B 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX8DXL_SPI0_SCK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX8DXL_SPI0_SDI 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX8DXL_SPI0_SDO 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX8DXL_SPI0_CS1 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX8DXL_SPI0_CS0 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX8DXL_ADC_IN1 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX8DXL_ADC_IN0 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX8DXL_ADC_IN3 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX8DXL_ADC_IN2 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX8DXL_ADC_IN5 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX8DXL_ADC_IN4 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX8DXL_FLEXCAN0_RX 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX8DXL_FLEXCAN0_TX 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX8DXL_FLEXCAN1_RX 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX8DXL_FLEXCAN1_TX 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX8DXL_FLEXCAN2_RX 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX8DXL_FLEXCAN2_TX 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX8DXL_UART0_RX 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX8DXL_UART0_TX 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX8DXL_UART2_TX 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX8DXL_UART2_RX 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX8DXL_JTAG_TRST_B 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX8DXL_PMIC_I2C_SCL 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX8DXL_PMIC_I2C_SDA 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX8DXL_PMIC_INT_B 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX8DXL_SCU_GPIO0_00 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX8DXL_SCU_GPIO0_01 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX8DXL_SCU_PMIC_STANDBY 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX8DXL_SCU_BOOT_MODE1 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX8DXL_SCU_BOOT_MODE0 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX8DXL_SCU_BOOT_MODE2 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX8DXL_SNVS_TAMPER_OUT1 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX8DXL_SNVS_TAMPER_OUT2 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX8DXL_SNVS_TAMPER_OUT3 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX8DXL_SNVS_TAMPER_OUT4 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX8DXL_SNVS_TAMPER_IN0 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX8DXL_SNVS_TAMPER_IN1 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX8DXL_SNVS_TAMPER_IN2 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX8DXL_SNVS_TAMPER_IN3 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX8DXL_SPI1_SCK 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX8DXL_SPI1_SDO 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX8DXL_SPI1_SDI 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX8DXL_SPI1_CS0 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX8DXL_QSPI0A_DATA1 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX8DXL_QSPI0A_DATA0 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX8DXL_QSPI0A_DATA3 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX8DXL_QSPI0A_DATA2 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX8DXL_QSPI0A_SS0_B 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX8DXL_QSPI0A_DQS 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX8DXL_QSPI0A_SCLK 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX8DXL_QSPI0B_SCLK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX8DXL_QSPI0B_DQS 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX8DXL_QSPI0B_DATA1 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX8DXL_QSPI0B_DATA0 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX8DXL_QSPI0B_DATA3 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX8DXL_QSPI0B_DATA2 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX8DXL_QSPI0B_SS0_B 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* format: <pin_id mux_mode> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX8DXL_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8DXL_PCIE_CTRL0_PERST_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO7_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX8DXL_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8DXL_PCIE_CTRL0_CLKREQ_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO7_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX8DXL_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8DXL_PCIE_CTRL0_WAKE_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO7_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX8DXL_USB_SS3_TC0_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8DXL_USB_SS3_TC0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8DXL_USB_SS3_TC0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX8DXL_USB_SS3_TC0_LSIO_GPIO7_IO03 IMX8DXL_USB_SS3_TC0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX8DXL_USB_SS3_TC1_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8DXL_USB_SS3_TC1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX8DXL_USB_SS3_TC1_LSIO_GPIO7_IO04 IMX8DXL_USB_SS3_TC1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX8DXL_USB_SS3_TC2_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8DXL_USB_SS3_TC2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8DXL_USB_SS3_TC2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX8DXL_USB_SS3_TC2_LSIO_GPIO7_IO05 IMX8DXL_USB_SS3_TC2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX8DXL_USB_SS3_TC3_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX8DXL_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8DXL_USB_SS3_TC3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX8DXL_USB_SS3_TC3_LSIO_GPIO7_IO06 IMX8DXL_USB_SS3_TC3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK IMX8DXL_EMMC0_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B IMX8DXL_EMMC0_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX8DXL_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8DXL_EMMC0_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD IMX8DXL_EMMC0_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX8DXL_EMMC0_CMD_CONN_NAND_DQS IMX8DXL_EMMC0_CMD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX8DXL_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8DXL_EMMC0_CMD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8DXL_EMMC0_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 IMX8DXL_EMMC0_DATA0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX8DXL_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8DXL_EMMC0_DATA0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8DXL_EMMC0_DATA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 IMX8DXL_EMMC0_DATA1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX8DXL_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8DXL_EMMC0_DATA1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8DXL_EMMC0_DATA2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 IMX8DXL_EMMC0_DATA2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX8DXL_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8DXL_EMMC0_DATA2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8DXL_EMMC0_DATA3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 IMX8DXL_EMMC0_DATA3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX8DXL_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8DXL_EMMC0_DATA3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8DXL_EMMC0_DATA4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 IMX8DXL_EMMC0_DATA4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX8DXL_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8DXL_EMMC0_DATA4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8DXL_EMMC0_DATA5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 IMX8DXL_EMMC0_DATA5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX8DXL_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8DXL_EMMC0_DATA5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8DXL_EMMC0_DATA6 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 IMX8DXL_EMMC0_DATA6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX8DXL_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8DXL_EMMC0_DATA6 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8DXL_EMMC0_DATA7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 IMX8DXL_EMMC0_DATA7 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX8DXL_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8DXL_EMMC0_DATA7 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8DXL_EMMC0_STROBE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE IMX8DXL_EMMC0_STROBE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX8DXL_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8DXL_EMMC0_STROBE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8DXL_EMMC0_RESET_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B IMX8DXL_EMMC0_RESET_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX8DXL_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8DXL_EMMC0_RESET_B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX8DXL_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8DXL_USDHC1_RESET_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX8DXL_USDHC1_RESET_B_CONN_NAND_RE_N IMX8DXL_USDHC1_RESET_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8DXL_USDHC1_RESET_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B IMX8DXL_USDHC1_RESET_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8DXL_USDHC1_RESET_B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO7_IO08 IMX8DXL_USDHC1_RESET_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMX8DXL_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8DXL_USDHC1_VSELECT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_P IMX8DXL_USDHC1_VSELECT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8DXL_USDHC1_VSELECT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B IMX8DXL_USDHC1_VSELECT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8DXL_USDHC1_VSELECT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO7_IO09 IMX8DXL_USDHC1_VSELECT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IMX8DXL_USDHC1_WP_CONN_USDHC1_WP IMX8DXL_USDHC1_WP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX8DXL_USDHC1_WP_CONN_NAND_DQS_N IMX8DXL_USDHC1_WP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI IMX8DXL_USDHC1_WP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX8DXL_USDHC1_WP_CONN_NAND_ALE IMX8DXL_USDHC1_WP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IMX8DXL_USDHC1_WP_LSIO_GPIO4_IO21 IMX8DXL_USDHC1_WP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX8DXL_USDHC1_WP_LSIO_GPIO7_IO10 IMX8DXL_USDHC1_WP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMX8DXL_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8DXL_USDHC1_CD_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS_P IMX8DXL_USDHC1_CD_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMX8DXL_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8DXL_USDHC1_CD_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS IMX8DXL_USDHC1_CD_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8DXL_USDHC1_CD_B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX8DXL_USDHC1_CD_B_LSIO_GPIO7_IO11 IMX8DXL_USDHC1_CD_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8DXL_ENET0_RGMII_TXC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8DXL_ENET0_RGMII_TXC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8DXL_ENET0_RGMII_TXC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX8DXL_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8DXL_ENET0_RGMII_TXC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IMX8DXL_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8DXL_ENET0_RGMII_TXC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK IMX8DXL_ENET0_RGMII_TXC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8DXL_ENET0_RGMII_TX_CTL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8DXL_ENET0_RGMII_TX_CTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8DXL_ENET0_RGMII_TX_CTL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD IMX8DXL_ENET0_RGMII_TX_CTL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8DXL_ENET0_RGMII_TXD0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8DXL_ENET0_RGMII_TXD0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IMX8DXL_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8DXL_ENET0_RGMII_TXD0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 IMX8DXL_ENET0_RGMII_TXD0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8DXL_ENET0_RGMII_TXD1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8DXL_ENET0_RGMII_TXD1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8DXL_ENET0_RGMII_TXD1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 IMX8DXL_ENET0_RGMII_TXD1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8DXL_ENET0_RGMII_TXD2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX8DXL_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8DXL_ENET0_RGMII_TXD2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8DXL_ENET0_RGMII_TXD2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8DXL_ENET0_RGMII_TXD2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 IMX8DXL_ENET0_RGMII_TXD2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8DXL_ENET0_RGMII_TXD3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IMX8DXL_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8DXL_ENET0_RGMII_TXD3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX8DXL_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8DXL_ENET0_RGMII_TXD3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 IMX8DXL_ENET0_RGMII_TXD3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8DXL_ENET0_RGMII_RXC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IMX8DXL_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8DXL_ENET0_RGMII_RXC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8DXL_ENET0_RGMII_RXC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IMX8DXL_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8DXL_ENET0_RGMII_RXC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8DXL_ENET0_RGMII_RX_CTL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8DXL_ENET0_RGMII_RX_CTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX8DXL_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8DXL_ENET0_RGMII_RX_CTL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8DXL_ENET0_RGMII_RXD0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8DXL_ENET0_RGMII_RXD0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMX8DXL_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8DXL_ENET0_RGMII_RXD0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8DXL_ENET0_RGMII_RXD1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8DXL_ENET0_RGMII_RXD1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IMX8DXL_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8DXL_ENET0_RGMII_RXD1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8DXL_ENET0_RGMII_RXD2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8DXL_ENET0_RGMII_RXD2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8DXL_ENET0_RGMII_RXD2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IMX8DXL_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8DXL_ENET0_RGMII_RXD2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8DXL_ENET0_RGMII_RXD3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IMX8DXL_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8DXL_ENET0_RGMII_RXD3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8DXL_ENET0_RGMII_RXD3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IMX8DXL_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8DXL_ENET0_RGMII_RXD3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8DXL_ENET0_REFCLK_125M_25M 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8DXL_ENET0_REFCLK_125M_25M 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_IN IMX8DXL_ENET0_REFCLK_125M_25M 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_OUT IMX8DXL_ENET0_REFCLK_125M_25M 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IMX8DXL_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8DXL_ENET0_REFCLK_125M_25M 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO IMX8DXL_ENET0_MDIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IMX8DXL_ENET0_MDIO_ADMA_I2C3_SDA IMX8DXL_ENET0_MDIO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO IMX8DXL_ENET0_MDIO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IMX8DXL_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8DXL_ENET0_MDIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IMX8DXL_ENET0_MDIO_LSIO_GPIO7_IO16 IMX8DXL_ENET0_MDIO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IMX8DXL_ENET0_MDC_CONN_ENET0_MDC IMX8DXL_ENET0_MDC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IMX8DXL_ENET0_MDC_ADMA_I2C3_SCL IMX8DXL_ENET0_MDC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IMX8DXL_ENET0_MDC_CONN_EQOS_MDC IMX8DXL_ENET0_MDC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IMX8DXL_ENET0_MDC_LSIO_GPIO5_IO11 IMX8DXL_ENET0_MDC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IMX8DXL_ENET0_MDC_LSIO_GPIO7_IO17 IMX8DXL_ENET0_MDC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IMX8DXL_ENET1_RGMII_TXC_LSIO_GPIO0_IO00 IMX8DXL_ENET1_RGMII_TXC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_OUT IMX8DXL_ENET1_RGMII_TXC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IMX8DXL_ENET1_RGMII_TXC_ADMA_LCDIF_D00 IMX8DXL_ENET1_RGMII_TXC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC IMX8DXL_ENET1_RGMII_TXC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_IN IMX8DXL_ENET1_RGMII_TXC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IMX8DXL_ENET1_RGMII_TXD2_ADMA_LCDIF_D01 IMX8DXL_ENET1_RGMII_TXD2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 IMX8DXL_ENET1_RGMII_TXD2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IMX8DXL_ENET1_RGMII_TXD2_LSIO_GPIO0_IO01 IMX8DXL_ENET1_RGMII_TXD2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IMX8DXL_ENET1_RGMII_TX_CTL_ADMA_LCDIF_D02 IMX8DXL_ENET1_RGMII_TX_CTL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL IMX8DXL_ENET1_RGMII_TX_CTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IMX8DXL_ENET1_RGMII_TX_CTL_LSIO_GPIO0_IO02 IMX8DXL_ENET1_RGMII_TX_CTL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 IMX8DXL_ENET1_RGMII_TXD3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 IMX8DXL_ENET1_RGMII_TXD3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IMX8DXL_ENET1_RGMII_TXD3_LSIO_GPIO0_IO03 IMX8DXL_ENET1_RGMII_TXD3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IMX8DXL_ENET1_RGMII_RXC_ADMA_LCDIF_D04 IMX8DXL_ENET1_RGMII_RXC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC IMX8DXL_ENET1_RGMII_RXC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IMX8DXL_ENET1_RGMII_RXC_LSIO_GPIO0_IO04 IMX8DXL_ENET1_RGMII_RXC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IMX8DXL_ENET1_RGMII_RXD3_ADMA_LCDIF_D05 IMX8DXL_ENET1_RGMII_RXD3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 IMX8DXL_ENET1_RGMII_RXD3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IMX8DXL_ENET1_RGMII_RXD3_LSIO_GPIO0_IO05 IMX8DXL_ENET1_RGMII_RXD3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IMX8DXL_ENET1_RGMII_RXD2_ADMA_LCDIF_D06 IMX8DXL_ENET1_RGMII_RXD2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 IMX8DXL_ENET1_RGMII_RXD2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO0_IO06 IMX8DXL_ENET1_RGMII_RXD2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO6_IO00 IMX8DXL_ENET1_RGMII_RXD2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IMX8DXL_ENET1_RGMII_RXD1_ADMA_LCDIF_D07 IMX8DXL_ENET1_RGMII_RXD1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 IMX8DXL_ENET1_RGMII_RXD1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO0_IO07 IMX8DXL_ENET1_RGMII_RXD1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO6_IO01 IMX8DXL_ENET1_RGMII_RXD1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IMX8DXL_ENET1_RGMII_TXD0_ADMA_LCDIF_D08 IMX8DXL_ENET1_RGMII_TXD0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 IMX8DXL_ENET1_RGMII_TXD0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO0_IO08 IMX8DXL_ENET1_RGMII_TXD0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO6_IO02 IMX8DXL_ENET1_RGMII_TXD0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IMX8DXL_ENET1_RGMII_TXD1_ADMA_LCDIF_D09 IMX8DXL_ENET1_RGMII_TXD1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 IMX8DXL_ENET1_RGMII_TXD1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO0_IO09 IMX8DXL_ENET1_RGMII_TXD1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO6_IO03 IMX8DXL_ENET1_RGMII_TXD1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IMX8DXL_ENET1_RGMII_RXD0_ADMA_SPDIF0_RX IMX8DXL_ENET1_RGMII_RXD0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IMX8DXL_ENET1_RGMII_RXD0_ADMA_MQS_R IMX8DXL_ENET1_RGMII_RXD0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IMX8DXL_ENET1_RGMII_RXD0_ADMA_LCDIF_D10 IMX8DXL_ENET1_RGMII_RXD0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 IMX8DXL_ENET1_RGMII_RXD0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO0_IO10 IMX8DXL_ENET1_RGMII_RXD0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO6_IO04 IMX8DXL_ENET1_RGMII_RXD0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_SPDIF0_TX IMX8DXL_ENET1_RGMII_RX_CTL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_MQS_L IMX8DXL_ENET1_RGMII_RX_CTL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_LCDIF_D11 IMX8DXL_ENET1_RGMII_RX_CTL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL IMX8DXL_ENET1_RGMII_RX_CTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO0_IO11 IMX8DXL_ENET1_RGMII_RX_CTL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8DXL_ENET1_RGMII_RX_CTL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_SPDIF0_EXT_CLK IMX8DXL_ENET1_REFCLK_125M_25M 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_LCDIF_D12 IMX8DXL_ENET1_REFCLK_125M_25M 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IMX8DXL_ENET1_REFCLK_125M_25M_CONN_EQOS_REFCLK_125M_25M IMX8DXL_ENET1_REFCLK_125M_25M 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO0_IO12 IMX8DXL_ENET1_REFCLK_125M_25M 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO6_IO06 IMX8DXL_ENET1_REFCLK_125M_25M 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK IMX8DXL_SPI3_SCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D13 IMX8DXL_SPI3_SCK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 IMX8DXL_SPI3_SCK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 IMX8DXL_SPI3_SCK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO IMX8DXL_SPI3_SDO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D14 IMX8DXL_SPI3_SDO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 IMX8DXL_SPI3_SDO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 IMX8DXL_SPI3_SDO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI IMX8DXL_SPI3_SDI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D15 IMX8DXL_SPI3_SDI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 IMX8DXL_SPI3_SDI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 IMX8DXL_SPI3_SDI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IMX8DXL_SPI3_CS0_ADMA_SPI3_CS0 IMX8DXL_SPI3_CS0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8DXL_SPI3_CS0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8DXL_SPI3_CS0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 IMX8DXL_SPI3_CS0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define IMX8DXL_SPI3_CS0_ADMA_LCDIF_CS IMX8DXL_SPI3_CS0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 IMX8DXL_SPI3_CS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define IMX8DXL_SPI3_CS1_ADMA_I2C3_SCL IMX8DXL_SPI3_CS1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET IMX8DXL_SPI3_CS1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IMX8DXL_SPI3_CS1_ADMA_SPI2_CS0 IMX8DXL_SPI3_CS1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define IMX8DXL_SPI3_CS1_ADMA_LCDIF_D16 IMX8DXL_SPI3_CS1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RD_E IMX8DXL_SPI3_CS1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define IMX8DXL_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8DXL_MCLK_IN1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define IMX8DXL_MCLK_IN1_ADMA_I2C3_SDA IMX8DXL_MCLK_IN1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN IMX8DXL_MCLK_IN1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IMX8DXL_MCLK_IN1_ADMA_SPI2_SCK IMX8DXL_MCLK_IN1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D17 IMX8DXL_MCLK_IN1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D03 IMX8DXL_MCLK_IN1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define IMX8DXL_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8DXL_MCLK_IN0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8DXL_MCLK_IN0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IMX8DXL_MCLK_IN0_ADMA_SPI2_SDI IMX8DXL_MCLK_IN0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IMX8DXL_MCLK_IN0_LSIO_GPIO0_IO19 IMX8DXL_MCLK_IN0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IMX8DXL_MCLK_IN0_ADMA_LCDIF_RS IMX8DXL_MCLK_IN0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8DXL_MCLK_OUT0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK IMX8DXL_MCLK_OUT0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define IMX8DXL_MCLK_OUT0_ADMA_SPI2_SDO IMX8DXL_MCLK_OUT0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8DXL_MCLK_OUT0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_WR_RWN IMX8DXL_MCLK_OUT0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IMX8DXL_UART1_TX_ADMA_UART1_TX IMX8DXL_UART1_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IMX8DXL_UART1_TX_LSIO_PWM0_OUT IMX8DXL_UART1_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IMX8DXL_UART1_TX_LSIO_GPT0_CAPTURE IMX8DXL_UART1_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IMX8DXL_UART1_TX_LSIO_GPIO0_IO21 IMX8DXL_UART1_TX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define IMX8DXL_UART1_TX_ADMA_LCDIF_D04 IMX8DXL_UART1_TX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define IMX8DXL_UART1_RX_ADMA_UART1_RX IMX8DXL_UART1_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define IMX8DXL_UART1_RX_LSIO_PWM1_OUT IMX8DXL_UART1_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IMX8DXL_UART1_RX_LSIO_GPT0_COMPARE IMX8DXL_UART1_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IMX8DXL_UART1_RX_LSIO_GPT1_CLK IMX8DXL_UART1_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define IMX8DXL_UART1_RX_LSIO_GPIO0_IO22 IMX8DXL_UART1_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define IMX8DXL_UART1_RX_ADMA_LCDIF_D05 IMX8DXL_UART1_RX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B IMX8DXL_UART1_RTS_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define IMX8DXL_UART1_RTS_B_LSIO_PWM2_OUT IMX8DXL_UART1_RTS_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D16 IMX8DXL_UART1_RTS_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define IMX8DXL_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8DXL_UART1_RTS_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define IMX8DXL_UART1_RTS_B_LSIO_GPT0_CLK IMX8DXL_UART1_RTS_B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 IMX8DXL_UART1_RTS_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B IMX8DXL_UART1_CTS_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define IMX8DXL_UART1_CTS_B_LSIO_PWM3_OUT IMX8DXL_UART1_CTS_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D17 IMX8DXL_UART1_CTS_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define IMX8DXL_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8DXL_UART1_CTS_B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define IMX8DXL_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8DXL_UART1_CTS_B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 IMX8DXL_UART1_CTS_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK IMX8DXL_SPI0_SCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC IMX8DXL_SPI0_SCK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define IMX8DXL_SPI0_SCK_M40_I2C0_SCL IMX8DXL_SPI0_SCK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define IMX8DXL_SPI0_SCK_M40_GPIO0_IO00 IMX8DXL_SPI0_SCK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define IMX8DXL_SPI0_SCK_LSIO_GPIO1_IO04 IMX8DXL_SPI0_SCK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 IMX8DXL_SPI0_SCK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI IMX8DXL_SPI0_SDI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD IMX8DXL_SPI0_SDI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define IMX8DXL_SPI0_SDI_M40_TPM0_CH0 IMX8DXL_SPI0_SDI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define IMX8DXL_SPI0_SDI_M40_GPIO0_IO02 IMX8DXL_SPI0_SDI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define IMX8DXL_SPI0_SDI_LSIO_GPIO1_IO05 IMX8DXL_SPI0_SDI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 IMX8DXL_SPI0_SDI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO IMX8DXL_SPI0_SDO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS IMX8DXL_SPI0_SDO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define IMX8DXL_SPI0_SDO_M40_I2C0_SDA IMX8DXL_SPI0_SDO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define IMX8DXL_SPI0_SDO_M40_GPIO0_IO01 IMX8DXL_SPI0_SDO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define IMX8DXL_SPI0_SDO_LSIO_GPIO1_IO06 IMX8DXL_SPI0_SDO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 IMX8DXL_SPI0_SDO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define IMX8DXL_SPI0_CS1_ADMA_SPI0_CS1 IMX8DXL_SPI0_CS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC IMX8DXL_SPI0_CS1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define IMX8DXL_SPI0_CS1_ADMA_SAI1_TXD IMX8DXL_SPI0_CS1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define IMX8DXL_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8DXL_SPI0_CS1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 IMX8DXL_SPI0_CS1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 IMX8DXL_SPI0_CS1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define IMX8DXL_SPI0_CS0_ADMA_SPI0_CS0 IMX8DXL_SPI0_CS0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD IMX8DXL_SPI0_CS0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define IMX8DXL_SPI0_CS0_M40_TPM0_CH1 IMX8DXL_SPI0_CS0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define IMX8DXL_SPI0_CS0_M40_GPIO0_IO03 IMX8DXL_SPI0_CS0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 IMX8DXL_SPI0_CS0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 IMX8DXL_SPI0_CS0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define IMX8DXL_ADC_IN1_ADMA_ADC_IN1 IMX8DXL_ADC_IN1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define IMX8DXL_ADC_IN1_M40_I2C0_SDA IMX8DXL_ADC_IN1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define IMX8DXL_ADC_IN1_M40_GPIO0_IO01 IMX8DXL_ADC_IN1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define IMX8DXL_ADC_IN1_ADMA_I2C0_SDA IMX8DXL_ADC_IN1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 IMX8DXL_ADC_IN1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 IMX8DXL_ADC_IN1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define IMX8DXL_ADC_IN0_ADMA_ADC_IN0 IMX8DXL_ADC_IN0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define IMX8DXL_ADC_IN0_M40_I2C0_SCL IMX8DXL_ADC_IN0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define IMX8DXL_ADC_IN0_M40_GPIO0_IO00 IMX8DXL_ADC_IN0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define IMX8DXL_ADC_IN0_ADMA_I2C0_SCL IMX8DXL_ADC_IN0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 IMX8DXL_ADC_IN0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 IMX8DXL_ADC_IN0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define IMX8DXL_ADC_IN3_ADMA_ADC_IN3 IMX8DXL_ADC_IN3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define IMX8DXL_ADC_IN3_M40_UART0_TX IMX8DXL_ADC_IN3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define IMX8DXL_ADC_IN3_M40_GPIO0_IO03 IMX8DXL_ADC_IN3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define IMX8DXL_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8DXL_ADC_IN3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 IMX8DXL_ADC_IN3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 IMX8DXL_ADC_IN3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define IMX8DXL_ADC_IN2_ADMA_ADC_IN2 IMX8DXL_ADC_IN2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define IMX8DXL_ADC_IN2_M40_UART0_RX IMX8DXL_ADC_IN2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define IMX8DXL_ADC_IN2_M40_GPIO0_IO02 IMX8DXL_ADC_IN2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define IMX8DXL_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8DXL_ADC_IN2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 IMX8DXL_ADC_IN2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 IMX8DXL_ADC_IN2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define IMX8DXL_ADC_IN5_ADMA_ADC_IN5 IMX8DXL_ADC_IN5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define IMX8DXL_ADC_IN5_M40_TPM0_CH1 IMX8DXL_ADC_IN5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define IMX8DXL_ADC_IN5_M40_GPIO0_IO05 IMX8DXL_ADC_IN5 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define IMX8DXL_ADC_IN5_ADMA_LCDIF_LCDBUSY IMX8DXL_ADC_IN5 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 IMX8DXL_ADC_IN5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 IMX8DXL_ADC_IN5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define IMX8DXL_ADC_IN4_ADMA_ADC_IN4 IMX8DXL_ADC_IN4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define IMX8DXL_ADC_IN4_M40_TPM0_CH0 IMX8DXL_ADC_IN4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define IMX8DXL_ADC_IN4_M40_GPIO0_IO04 IMX8DXL_ADC_IN4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define IMX8DXL_ADC_IN4_ADMA_LCDIF_LCDRESET IMX8DXL_ADC_IN4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 IMX8DXL_ADC_IN4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8DXL_FLEXCAN0_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define IMX8DXL_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8DXL_FLEXCAN0_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define IMX8DXL_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8DXL_FLEXCAN0_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8DXL_FLEXCAN0_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8DXL_FLEXCAN0_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO6_IO08 IMX8DXL_FLEXCAN0_RX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8DXL_FLEXCAN0_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define IMX8DXL_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8DXL_FLEXCAN0_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define IMX8DXL_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8DXL_FLEXCAN0_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8DXL_FLEXCAN0_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8DXL_FLEXCAN0_TX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO6_IO09 IMX8DXL_FLEXCAN0_TX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8DXL_FLEXCAN1_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define IMX8DXL_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8DXL_FLEXCAN1_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define IMX8DXL_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8DXL_FLEXCAN1_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8DXL_FLEXCAN1_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8DXL_FLEXCAN1_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO6_IO10 IMX8DXL_FLEXCAN1_RX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8DXL_FLEXCAN1_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define IMX8DXL_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8DXL_FLEXCAN1_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define IMX8DXL_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8DXL_FLEXCAN1_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8DXL_FLEXCAN1_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8DXL_FLEXCAN1_TX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO6_IO11 IMX8DXL_FLEXCAN1_TX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8DXL_FLEXCAN2_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define IMX8DXL_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8DXL_FLEXCAN2_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define IMX8DXL_FLEXCAN2_RX_ADMA_UART3_RX IMX8DXL_FLEXCAN2_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define IMX8DXL_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8DXL_FLEXCAN2_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8DXL_FLEXCAN2_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO6_IO12 IMX8DXL_FLEXCAN2_RX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8DXL_FLEXCAN2_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define IMX8DXL_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8DXL_FLEXCAN2_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define IMX8DXL_FLEXCAN2_TX_ADMA_UART3_TX IMX8DXL_FLEXCAN2_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define IMX8DXL_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8DXL_FLEXCAN2_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8DXL_FLEXCAN2_TX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO6_IO13 IMX8DXL_FLEXCAN2_TX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define IMX8DXL_UART0_RX_ADMA_UART0_RX IMX8DXL_UART0_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define IMX8DXL_UART0_RX_ADMA_MQS_R IMX8DXL_UART0_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define IMX8DXL_UART0_RX_ADMA_FLEXCAN0_RX IMX8DXL_UART0_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define IMX8DXL_UART0_RX_SCU_UART0_RX IMX8DXL_UART0_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define IMX8DXL_UART0_RX_LSIO_GPIO1_IO21 IMX8DXL_UART0_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define IMX8DXL_UART0_RX_LSIO_GPIO6_IO14 IMX8DXL_UART0_RX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define IMX8DXL_UART0_TX_ADMA_UART0_TX IMX8DXL_UART0_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define IMX8DXL_UART0_TX_ADMA_MQS_L IMX8DXL_UART0_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define IMX8DXL_UART0_TX_ADMA_FLEXCAN0_TX IMX8DXL_UART0_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define IMX8DXL_UART0_TX_SCU_UART0_TX IMX8DXL_UART0_TX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define IMX8DXL_UART0_TX_LSIO_GPIO1_IO22 IMX8DXL_UART0_TX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define IMX8DXL_UART0_TX_LSIO_GPIO6_IO15 IMX8DXL_UART0_TX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define IMX8DXL_UART2_TX_ADMA_UART2_TX IMX8DXL_UART2_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define IMX8DXL_UART2_TX_ADMA_FTM_CH1 IMX8DXL_UART2_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX IMX8DXL_UART2_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define IMX8DXL_UART2_TX_LSIO_GPIO1_IO23 IMX8DXL_UART2_TX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define IMX8DXL_UART2_TX_LSIO_GPIO6_IO16 IMX8DXL_UART2_TX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define IMX8DXL_UART2_RX_ADMA_UART2_RX IMX8DXL_UART2_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define IMX8DXL_UART2_RX_ADMA_FTM_CH0 IMX8DXL_UART2_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX IMX8DXL_UART2_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define IMX8DXL_UART2_RX_LSIO_GPIO1_IO24 IMX8DXL_UART2_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define IMX8DXL_UART2_RX_LSIO_GPIO6_IO17 IMX8DXL_UART2_RX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define IMX8DXL_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8DXL_JTAG_TRST_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define IMX8DXL_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8DXL_JTAG_TRST_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define IMX8DXL_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8DXL_PMIC_I2C_SCL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define IMX8DXL_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8DXL_PMIC_I2C_SCL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define IMX8DXL_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8DXL_PMIC_I2C_SCL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define IMX8DXL_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8DXL_PMIC_I2C_SDA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define IMX8DXL_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8DXL_PMIC_I2C_SDA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define IMX8DXL_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8DXL_PMIC_I2C_SDA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define IMX8DXL_PMIC_INT_B_SCU_DSC_PMIC_INT_B IMX8DXL_PMIC_INT_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define IMX8DXL_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8DXL_SCU_GPIO0_00 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define IMX8DXL_SCU_GPIO0_00_SCU_UART0_RX IMX8DXL_SCU_GPIO0_00 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define IMX8DXL_SCU_GPIO0_00_M40_UART0_RX IMX8DXL_SCU_GPIO0_00 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define IMX8DXL_SCU_GPIO0_00_ADMA_UART3_RX IMX8DXL_SCU_GPIO0_00 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define IMX8DXL_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8DXL_SCU_GPIO0_00 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define IMX8DXL_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8DXL_SCU_GPIO0_01 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define IMX8DXL_SCU_GPIO0_01_SCU_UART0_TX IMX8DXL_SCU_GPIO0_01 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define IMX8DXL_SCU_GPIO0_01_M40_UART0_TX IMX8DXL_SCU_GPIO0_01 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define IMX8DXL_SCU_GPIO0_01_ADMA_UART3_TX IMX8DXL_SCU_GPIO0_01 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define IMX8DXL_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8DXL_SCU_GPIO0_01 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define IMX8DXL_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY IMX8DXL_SCU_PMIC_STANDBY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define IMX8DXL_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8DXL_SCU_BOOT_MODE1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define IMX8DXL_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8DXL_SCU_BOOT_MODE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8DXL_SCU_BOOT_MODE2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8DXL_SCU_BOOT_MODE2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN IMX8DXL_SNVS_TAMPER_OUT1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO6_IO19_IN IMX8DXL_SNVS_TAMPER_OUT1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN IMX8DXL_SNVS_TAMPER_OUT2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO6_IO20_IN IMX8DXL_SNVS_TAMPER_OUT2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC IMX8DXL_SNVS_TAMPER_OUT3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO2_IO07_IN IMX8DXL_SNVS_TAMPER_OUT3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO6_IO21_IN IMX8DXL_SNVS_TAMPER_OUT3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD IMX8DXL_SNVS_TAMPER_OUT4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN IMX8DXL_SNVS_TAMPER_OUT4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO6_IO22_IN IMX8DXL_SNVS_TAMPER_OUT4 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS IMX8DXL_SNVS_TAMPER_IN0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN IMX8DXL_SNVS_TAMPER_IN0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO6_IO23_IN IMX8DXL_SNVS_TAMPER_IN0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC IMX8DXL_SNVS_TAMPER_IN1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN IMX8DXL_SNVS_TAMPER_IN1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO6_IO24_IN IMX8DXL_SNVS_TAMPER_IN1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD IMX8DXL_SNVS_TAMPER_IN2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN IMX8DXL_SNVS_TAMPER_IN2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO6_IO25_IN IMX8DXL_SNVS_TAMPER_IN2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS IMX8DXL_SNVS_TAMPER_IN3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO2_IO12_IN IMX8DXL_SNVS_TAMPER_IN3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO6_IO26_IN IMX8DXL_SNVS_TAMPER_IN3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA IMX8DXL_SPI1_SCK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define IMX8DXL_SPI1_SCK_ADMA_SPI1_SCK IMX8DXL_SPI1_SCK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 IMX8DXL_SPI1_SCK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL IMX8DXL_SPI1_SDO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define IMX8DXL_SPI1_SDO_ADMA_SPI1_SDO IMX8DXL_SPI1_SDO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 IMX8DXL_SPI1_SDO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL IMX8DXL_SPI1_SDI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define IMX8DXL_SPI1_SDI_ADMA_SPI1_SDI IMX8DXL_SPI1_SDI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 IMX8DXL_SPI1_SDI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA IMX8DXL_SPI1_CS0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define IMX8DXL_SPI1_CS0_ADMA_SPI1_CS0 IMX8DXL_SPI1_CS0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 IMX8DXL_SPI1_CS0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8DXL_QSPI0A_DATA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define IMX8DXL_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8DXL_QSPI0A_DATA1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8DXL_QSPI0A_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define IMX8DXL_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8DXL_QSPI0A_DATA0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8DXL_QSPI0A_DATA3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define IMX8DXL_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8DXL_QSPI0A_DATA3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8DXL_QSPI0A_DATA2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define IMX8DXL_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8DXL_QSPI0A_DATA2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8DXL_QSPI0A_SS0_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define IMX8DXL_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8DXL_QSPI0A_SS0_B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8DXL_QSPI0A_DQS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define IMX8DXL_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8DXL_QSPI0A_DQS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8DXL_QSPI0A_SCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define IMX8DXL_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8DXL_QSPI0A_SCLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8DXL_QSPI0B_SCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define IMX8DXL_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8DXL_QSPI0B_SCLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8DXL_QSPI0B_DQS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define IMX8DXL_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8DXL_QSPI0B_DQS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8DXL_QSPI0B_DATA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8DXL_QSPI0B_DATA1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8DXL_QSPI0B_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8DXL_QSPI0B_DATA0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8DXL_QSPI0B_DATA3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8DXL_QSPI0B_DATA3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8DXL_QSPI0B_DATA2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8DXL_QSPI0B_DATA2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8DXL_QSPI0B_SS0_B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define IMX8DXL_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8DXL_QSPI0B_SS0_B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0A_SS1_B IMX8DXL_QSPI0B_SS0_B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO_PAD IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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