^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This header provides constants for OMAP pinctrl bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Nokia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2010 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _DT_BINDINGS_PINCTRL_OMAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DT_BINDINGS_PINCTRL_OMAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* 34xx mux mode options for each pin. See TRM for options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MUX_MODE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MUX_MODE1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MUX_MODE2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MUX_MODE3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MUX_MODE4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MUX_MODE5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MUX_MODE6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MUX_MODE7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* 24xx/34xx mux bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PULL_ENA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PULL_UP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ALTELECTRICALSEL (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* omap3/4/5 specific mux bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define INPUT_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OFF_EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OFFOUT_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OFFOUT_VAL (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OFF_PULL_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OFF_PULL_UP (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WAKEUP_EN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WAKEUP_EVENT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Active pin states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PIN_OUTPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PIN_INPUT INPUT_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Off mode states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PIN_OFF_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PIN_OFF_INPUT_PULLUP (OFF_EN | OFFOUT_EN | OFF_PULL_EN | OFF_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFFOUT_EN | OFF_PULL_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PIN_OFF_WAKEUPENABLE WAKEUP_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Macros to allow using the absolute physical address instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * padconf registers instead of the offset from padconf base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Macros to allow using the offset from the padconf physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * instead of the offset from padconf base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Define some commonly used pins configured by the boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Note that some boards use alternative pins, so check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * the schematics before using these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP3_UART1_RX 0x152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP3_UART2_RX 0x14a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP3_UART3_RX 0x16e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP4_UART2_RX 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP4_UART3_RX 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP4_UART4_RX 0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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