Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_PINCTRL_MT65XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_PINCTRL_MT65XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MTK_PIN_NO(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MTK_GET_PIN_NO(x) ((x) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MTK_GET_PIN_FUNC(x) ((x) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MTK_PUPD_SET_R1R0_00 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MTK_PUPD_SET_R1R0_01 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MTK_PUPD_SET_R1R0_10 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MTK_PUPD_SET_R1R0_11 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MTK_DRIVE_2mA  2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MTK_DRIVE_4mA  4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MTK_DRIVE_6mA  6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MTK_DRIVE_8mA  8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MTK_DRIVE_10mA 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MTK_DRIVE_12mA 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MTK_DRIVE_14mA 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MTK_DRIVE_16mA 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MTK_DRIVE_20mA 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MTK_DRIVE_24mA 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MTK_DRIVE_28mA 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MTK_DRIVE_32mA 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */