Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __DTS_MT6397_PINFUNC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __DTS_MT6397_PINFUNC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <dt-bindings/pinctrl/mt65xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define MT6397_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define MT6397_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define MT6397_PIN_1_SRCVOLTEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define MT6397_PIN_1_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define MT6397_PIN_1_SRCVOLTEN__FUNC_TEST_CK1 (MTK_PIN_NO(1) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define MT6397_PIN_2_SRCLKEN_PERI__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MT6397_PIN_2_SRCLKEN_PERI__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MT6397_PIN_2_SRCLKEN_PERI__FUNC_TEST_CK2 (MTK_PIN_NO(2) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MT6397_PIN_3_RTC_32K1V8__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MT6397_PIN_3_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(3) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MT6397_PIN_3_RTC_32K1V8__FUNC_TEST_CK3 (MTK_PIN_NO(3) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MT6397_PIN_4_WRAP_EVENT__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MT6397_PIN_4_WRAP_EVENT__FUNC_WRAP_EVENT (MTK_PIN_NO(4) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MT6397_PIN_5_SPI_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MT6397_PIN_5_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(5) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MT6397_PIN_6_SPI_CSN__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MT6397_PIN_6_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(6) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MT6397_PIN_7_SPI_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MT6397_PIN_7_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(7) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MT6397_PIN_8_SPI_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MT6397_PIN_8_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(8) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(9) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_IN0 (MTK_PIN_NO(9) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_OUT0 (MTK_PIN_NO(9) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MT6397_PIN_10_AUD_DAT_MISO__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MT6397_PIN_10_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(10) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_IN1 (MTK_PIN_NO(10) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_OUT1 (MTK_PIN_NO(10) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(11) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_IN2 (MTK_PIN_NO(11) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_OUT2 (MTK_PIN_NO(11) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MT6397_PIN_12_COL0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MT6397_PIN_12_COL0__FUNC_COL0_USBDL (MTK_PIN_NO(12) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MT6397_PIN_12_COL0__FUNC_EINT10_1X (MTK_PIN_NO(12) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MT6397_PIN_12_COL0__FUNC_PWM1_3X (MTK_PIN_NO(12) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MT6397_PIN_12_COL0__FUNC_TEST_IN3 (MTK_PIN_NO(12) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MT6397_PIN_12_COL0__FUNC_TEST_OUT3 (MTK_PIN_NO(12) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MT6397_PIN_13_COL1__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MT6397_PIN_13_COL1__FUNC_COL1 (MTK_PIN_NO(13) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MT6397_PIN_13_COL1__FUNC_EINT11_1X (MTK_PIN_NO(13) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MT6397_PIN_13_COL1__FUNC_SCL0_2X (MTK_PIN_NO(13) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MT6397_PIN_13_COL1__FUNC_TEST_IN4 (MTK_PIN_NO(13) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MT6397_PIN_13_COL1__FUNC_TEST_OUT4 (MTK_PIN_NO(13) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MT6397_PIN_14_COL2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MT6397_PIN_14_COL2__FUNC_COL2 (MTK_PIN_NO(14) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MT6397_PIN_14_COL2__FUNC_EINT12_1X (MTK_PIN_NO(14) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MT6397_PIN_14_COL2__FUNC_SDA0_2X (MTK_PIN_NO(14) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MT6397_PIN_14_COL2__FUNC_TEST_IN5 (MTK_PIN_NO(14) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MT6397_PIN_14_COL2__FUNC_TEST_OUT5 (MTK_PIN_NO(14) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MT6397_PIN_15_COL3__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MT6397_PIN_15_COL3__FUNC_COL3 (MTK_PIN_NO(15) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MT6397_PIN_15_COL3__FUNC_EINT13_1X (MTK_PIN_NO(15) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MT6397_PIN_15_COL3__FUNC_SCL1_2X (MTK_PIN_NO(15) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MT6397_PIN_15_COL3__FUNC_TEST_IN6 (MTK_PIN_NO(15) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MT6397_PIN_15_COL3__FUNC_TEST_OUT6 (MTK_PIN_NO(15) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MT6397_PIN_16_COL4__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MT6397_PIN_16_COL4__FUNC_COL4 (MTK_PIN_NO(16) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MT6397_PIN_16_COL4__FUNC_EINT14_1X (MTK_PIN_NO(16) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MT6397_PIN_16_COL4__FUNC_SDA1_2X (MTK_PIN_NO(16) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MT6397_PIN_16_COL4__FUNC_TEST_IN7 (MTK_PIN_NO(16) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MT6397_PIN_16_COL4__FUNC_TEST_OUT7 (MTK_PIN_NO(16) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MT6397_PIN_17_COL5__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MT6397_PIN_17_COL5__FUNC_COL5 (MTK_PIN_NO(17) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MT6397_PIN_17_COL5__FUNC_EINT15_1X (MTK_PIN_NO(17) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MT6397_PIN_17_COL5__FUNC_SCL2_2X (MTK_PIN_NO(17) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MT6397_PIN_17_COL5__FUNC_TEST_IN8 (MTK_PIN_NO(17) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MT6397_PIN_17_COL5__FUNC_TEST_OUT8 (MTK_PIN_NO(17) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MT6397_PIN_18_COL6__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MT6397_PIN_18_COL6__FUNC_COL6 (MTK_PIN_NO(18) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MT6397_PIN_18_COL6__FUNC_EINT16_1X (MTK_PIN_NO(18) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MT6397_PIN_18_COL6__FUNC_SDA2_2X (MTK_PIN_NO(18) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MT6397_PIN_18_COL6__FUNC_GPIO32K_0 (MTK_PIN_NO(18) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MT6397_PIN_18_COL6__FUNC_GPIO26M_0 (MTK_PIN_NO(18) | 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MT6397_PIN_18_COL6__FUNC_TEST_IN9 (MTK_PIN_NO(18) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MT6397_PIN_18_COL6__FUNC_TEST_OUT9 (MTK_PIN_NO(18) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MT6397_PIN_19_COL7__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MT6397_PIN_19_COL7__FUNC_COL7 (MTK_PIN_NO(19) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MT6397_PIN_19_COL7__FUNC_EINT17_1X (MTK_PIN_NO(19) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MT6397_PIN_19_COL7__FUNC_PWM2_3X (MTK_PIN_NO(19) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MT6397_PIN_19_COL7__FUNC_GPIO32K_1 (MTK_PIN_NO(19) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MT6397_PIN_19_COL7__FUNC_GPIO26M_1 (MTK_PIN_NO(19) | 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MT6397_PIN_19_COL7__FUNC_TEST_IN10 (MTK_PIN_NO(19) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MT6397_PIN_19_COL7__FUNC_TEST_OUT10 (MTK_PIN_NO(19) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MT6397_PIN_20_ROW0__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MT6397_PIN_20_ROW0__FUNC_ROW0 (MTK_PIN_NO(20) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MT6397_PIN_20_ROW0__FUNC_EINT18_1X (MTK_PIN_NO(20) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MT6397_PIN_20_ROW0__FUNC_SCL0_3X (MTK_PIN_NO(20) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MT6397_PIN_20_ROW0__FUNC_TEST_IN11 (MTK_PIN_NO(20) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MT6397_PIN_20_ROW0__FUNC_TEST_OUT11 (MTK_PIN_NO(20) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MT6397_PIN_21_ROW1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MT6397_PIN_21_ROW1__FUNC_ROW1 (MTK_PIN_NO(21) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MT6397_PIN_21_ROW1__FUNC_EINT19_1X (MTK_PIN_NO(21) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MT6397_PIN_21_ROW1__FUNC_SDA0_3X (MTK_PIN_NO(21) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MT6397_PIN_21_ROW1__FUNC_AUD_TSTCK (MTK_PIN_NO(21) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MT6397_PIN_21_ROW1__FUNC_TEST_IN12 (MTK_PIN_NO(21) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MT6397_PIN_21_ROW1__FUNC_TEST_OUT12 (MTK_PIN_NO(21) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MT6397_PIN_22_ROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MT6397_PIN_22_ROW2__FUNC_ROW2 (MTK_PIN_NO(22) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MT6397_PIN_22_ROW2__FUNC_EINT20_1X (MTK_PIN_NO(22) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MT6397_PIN_22_ROW2__FUNC_SCL1_3X (MTK_PIN_NO(22) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MT6397_PIN_22_ROW2__FUNC_TEST_IN13 (MTK_PIN_NO(22) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MT6397_PIN_22_ROW2__FUNC_TEST_OUT13 (MTK_PIN_NO(22) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MT6397_PIN_23_ROW3__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MT6397_PIN_23_ROW3__FUNC_ROW3 (MTK_PIN_NO(23) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MT6397_PIN_23_ROW3__FUNC_EINT21_1X (MTK_PIN_NO(23) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MT6397_PIN_23_ROW3__FUNC_SDA1_3X (MTK_PIN_NO(23) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MT6397_PIN_23_ROW3__FUNC_TEST_IN14 (MTK_PIN_NO(23) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MT6397_PIN_23_ROW3__FUNC_TEST_OUT14 (MTK_PIN_NO(23) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MT6397_PIN_24_ROW4__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MT6397_PIN_24_ROW4__FUNC_ROW4 (MTK_PIN_NO(24) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MT6397_PIN_24_ROW4__FUNC_EINT22_1X (MTK_PIN_NO(24) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MT6397_PIN_24_ROW4__FUNC_SCL2_3X (MTK_PIN_NO(24) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MT6397_PIN_24_ROW4__FUNC_TEST_IN15 (MTK_PIN_NO(24) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MT6397_PIN_24_ROW4__FUNC_TEST_OUT15 (MTK_PIN_NO(24) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MT6397_PIN_25_ROW5__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MT6397_PIN_25_ROW5__FUNC_ROW5 (MTK_PIN_NO(25) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MT6397_PIN_25_ROW5__FUNC_EINT23_1X (MTK_PIN_NO(25) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MT6397_PIN_25_ROW5__FUNC_SDA2_3X (MTK_PIN_NO(25) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MT6397_PIN_25_ROW5__FUNC_TEST_IN16 (MTK_PIN_NO(25) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MT6397_PIN_25_ROW5__FUNC_TEST_OUT16 (MTK_PIN_NO(25) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MT6397_PIN_26_ROW6__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MT6397_PIN_26_ROW6__FUNC_ROW6 (MTK_PIN_NO(26) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MT6397_PIN_26_ROW6__FUNC_EINT24_1X (MTK_PIN_NO(26) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MT6397_PIN_26_ROW6__FUNC_PWM3_3X (MTK_PIN_NO(26) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MT6397_PIN_26_ROW6__FUNC_GPIO32K_2 (MTK_PIN_NO(26) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MT6397_PIN_26_ROW6__FUNC_GPIO26M_2 (MTK_PIN_NO(26) | 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MT6397_PIN_26_ROW6__FUNC_TEST_IN17 (MTK_PIN_NO(26) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MT6397_PIN_26_ROW6__FUNC_TEST_OUT17 (MTK_PIN_NO(26) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MT6397_PIN_27_ROW7__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MT6397_PIN_27_ROW7__FUNC_ROW7 (MTK_PIN_NO(27) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MT6397_PIN_27_ROW7__FUNC_EINT3_1X (MTK_PIN_NO(27) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MT6397_PIN_27_ROW7__FUNC_CBUS (MTK_PIN_NO(27) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MT6397_PIN_27_ROW7__FUNC_GPIO32K_3 (MTK_PIN_NO(27) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MT6397_PIN_27_ROW7__FUNC_GPIO26M_3 (MTK_PIN_NO(27) | 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MT6397_PIN_27_ROW7__FUNC_TEST_IN18 (MTK_PIN_NO(27) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MT6397_PIN_27_ROW7__FUNC_TEST_OUT18 (MTK_PIN_NO(27) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MT6397_PIN_28_PWM1__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MT6397_PIN_28_PWM1__FUNC_PWM1 (MTK_PIN_NO(28) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MT6397_PIN_28_PWM1__FUNC_EINT4_1X (MTK_PIN_NO(28) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MT6397_PIN_28_PWM1__FUNC_GPIO32K_4 (MTK_PIN_NO(28) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MT6397_PIN_28_PWM1__FUNC_GPIO26M_4 (MTK_PIN_NO(28) | 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MT6397_PIN_28_PWM1__FUNC_TEST_IN19 (MTK_PIN_NO(28) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MT6397_PIN_28_PWM1__FUNC_TEST_OUT19 (MTK_PIN_NO(28) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MT6397_PIN_29_PWM2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MT6397_PIN_29_PWM2__FUNC_PWM2 (MTK_PIN_NO(29) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MT6397_PIN_29_PWM2__FUNC_EINT5_1X (MTK_PIN_NO(29) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MT6397_PIN_29_PWM2__FUNC_GPIO32K_5 (MTK_PIN_NO(29) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MT6397_PIN_29_PWM2__FUNC_GPIO26M_5 (MTK_PIN_NO(29) | 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MT6397_PIN_29_PWM2__FUNC_TEST_IN20 (MTK_PIN_NO(29) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MT6397_PIN_29_PWM2__FUNC_TEST_OUT20 (MTK_PIN_NO(29) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MT6397_PIN_30_PWM3__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MT6397_PIN_30_PWM3__FUNC_PWM3 (MTK_PIN_NO(30) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MT6397_PIN_30_PWM3__FUNC_EINT6_1X (MTK_PIN_NO(30) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MT6397_PIN_30_PWM3__FUNC_COL0 (MTK_PIN_NO(30) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MT6397_PIN_30_PWM3__FUNC_GPIO32K_6 (MTK_PIN_NO(30) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MT6397_PIN_30_PWM3__FUNC_GPIO26M_6 (MTK_PIN_NO(30) | 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MT6397_PIN_30_PWM3__FUNC_TEST_IN21 (MTK_PIN_NO(30) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MT6397_PIN_30_PWM3__FUNC_TEST_OUT21 (MTK_PIN_NO(30) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MT6397_PIN_31_SCL0__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MT6397_PIN_31_SCL0__FUNC_SCL0 (MTK_PIN_NO(31) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MT6397_PIN_31_SCL0__FUNC_EINT7_1X (MTK_PIN_NO(31) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MT6397_PIN_31_SCL0__FUNC_PWM1_2X (MTK_PIN_NO(31) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MT6397_PIN_31_SCL0__FUNC_TEST_IN22 (MTK_PIN_NO(31) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MT6397_PIN_31_SCL0__FUNC_TEST_OUT22 (MTK_PIN_NO(31) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MT6397_PIN_32_SDA0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MT6397_PIN_32_SDA0__FUNC_SDA0 (MTK_PIN_NO(32) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MT6397_PIN_32_SDA0__FUNC_EINT8_1X (MTK_PIN_NO(32) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MT6397_PIN_32_SDA0__FUNC_TEST_IN23 (MTK_PIN_NO(32) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MT6397_PIN_32_SDA0__FUNC_TEST_OUT23 (MTK_PIN_NO(32) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MT6397_PIN_33_SCL1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MT6397_PIN_33_SCL1__FUNC_SCL1 (MTK_PIN_NO(33) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MT6397_PIN_33_SCL1__FUNC_EINT9_1X (MTK_PIN_NO(33) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MT6397_PIN_33_SCL1__FUNC_PWM2_2X (MTK_PIN_NO(33) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MT6397_PIN_33_SCL1__FUNC_TEST_IN24 (MTK_PIN_NO(33) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MT6397_PIN_33_SCL1__FUNC_TEST_OUT24 (MTK_PIN_NO(33) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MT6397_PIN_34_SDA1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MT6397_PIN_34_SDA1__FUNC_SDA1 (MTK_PIN_NO(34) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MT6397_PIN_34_SDA1__FUNC_EINT0_1X (MTK_PIN_NO(34) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MT6397_PIN_34_SDA1__FUNC_TEST_IN25 (MTK_PIN_NO(34) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MT6397_PIN_34_SDA1__FUNC_TEST_OUT25 (MTK_PIN_NO(34) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MT6397_PIN_35_SCL2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MT6397_PIN_35_SCL2__FUNC_SCL2 (MTK_PIN_NO(35) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MT6397_PIN_35_SCL2__FUNC_EINT1_1X (MTK_PIN_NO(35) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MT6397_PIN_35_SCL2__FUNC_PWM3_2X (MTK_PIN_NO(35) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MT6397_PIN_35_SCL2__FUNC_TEST_IN26 (MTK_PIN_NO(35) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MT6397_PIN_35_SCL2__FUNC_TEST_OUT26 (MTK_PIN_NO(35) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MT6397_PIN_36_SDA2__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MT6397_PIN_36_SDA2__FUNC_SDA2 (MTK_PIN_NO(36) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MT6397_PIN_36_SDA2__FUNC_EINT2_1X (MTK_PIN_NO(36) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MT6397_PIN_36_SDA2__FUNC_TEST_IN27 (MTK_PIN_NO(36) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MT6397_PIN_36_SDA2__FUNC_TEST_OUT27 (MTK_PIN_NO(36) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MT6397_PIN_37_HDMISD__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MT6397_PIN_37_HDMISD__FUNC_HDMISD (MTK_PIN_NO(37) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MT6397_PIN_37_HDMISD__FUNC_TEST_IN28 (MTK_PIN_NO(37) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MT6397_PIN_37_HDMISD__FUNC_TEST_OUT28 (MTK_PIN_NO(37) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MT6397_PIN_38_HDMISCK__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MT6397_PIN_38_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(38) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MT6397_PIN_38_HDMISCK__FUNC_TEST_IN29 (MTK_PIN_NO(38) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MT6397_PIN_38_HDMISCK__FUNC_TEST_OUT29 (MTK_PIN_NO(38) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MT6397_PIN_39_HTPLG__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MT6397_PIN_39_HTPLG__FUNC_HTPLG (MTK_PIN_NO(39) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MT6397_PIN_39_HTPLG__FUNC_TEST_IN30 (MTK_PIN_NO(39) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MT6397_PIN_39_HTPLG__FUNC_TEST_OUT30 (MTK_PIN_NO(39) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MT6397_PIN_40_CEC__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MT6397_PIN_40_CEC__FUNC_CEC (MTK_PIN_NO(40) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MT6397_PIN_40_CEC__FUNC_TEST_IN31 (MTK_PIN_NO(40) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MT6397_PIN_40_CEC__FUNC_TEST_OUT31 (MTK_PIN_NO(40) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif /* __DTS_MT6397_PINFUNC_H */