^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Device Tree defines for Lochnagar pinctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 Cirrus Logic, Inc. and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Cirrus Logic International Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef DT_BINDINGS_PINCTRL_LOCHNAGAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DT_BINDINGS_PINCTRL_LOCHNAGAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LOCHNAGAR1_PIN_CDC_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define LOCHNAGAR1_PIN_DSP_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LOCHNAGAR1_PIN_CDC_CIF1MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LOCHNAGAR1_PIN_NUM_GPIOS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LOCHNAGAR2_PIN_CDC_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LOCHNAGAR2_PIN_DSP_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LOCHNAGAR2_PIN_CDC_CIF1MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LOCHNAGAR2_PIN_CDC_LDOENA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LOCHNAGAR2_PIN_SPDIF_HWMODE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LOCHNAGAR2_PIN_SPDIF_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LOCHNAGAR2_PIN_FPGA_GPIO1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LOCHNAGAR2_PIN_FPGA_GPIO2 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LOCHNAGAR2_PIN_FPGA_GPIO3 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LOCHNAGAR2_PIN_FPGA_GPIO4 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LOCHNAGAR2_PIN_FPGA_GPIO5 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LOCHNAGAR2_PIN_FPGA_GPIO6 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LOCHNAGAR2_PIN_CDC_GPIO1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LOCHNAGAR2_PIN_CDC_GPIO2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LOCHNAGAR2_PIN_CDC_GPIO3 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LOCHNAGAR2_PIN_CDC_GPIO4 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LOCHNAGAR2_PIN_CDC_GPIO5 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LOCHNAGAR2_PIN_CDC_GPIO6 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LOCHNAGAR2_PIN_CDC_GPIO7 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LOCHNAGAR2_PIN_CDC_GPIO8 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LOCHNAGAR2_PIN_DSP_GPIO1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LOCHNAGAR2_PIN_DSP_GPIO2 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LOCHNAGAR2_PIN_DSP_GPIO3 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LOCHNAGAR2_PIN_DSP_GPIO4 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LOCHNAGAR2_PIN_DSP_GPIO5 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LOCHNAGAR2_PIN_DSP_GPIO6 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LOCHNAGAR2_PIN_GF_GPIO2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LOCHNAGAR2_PIN_GF_GPIO3 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LOCHNAGAR2_PIN_GF_GPIO7 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LOCHNAGAR2_PIN_CDC_AIF1_BCLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LOCHNAGAR2_PIN_CDC_AIF1_RXDAT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LOCHNAGAR2_PIN_CDC_AIF1_LRCLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LOCHNAGAR2_PIN_CDC_AIF1_TXDAT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LOCHNAGAR2_PIN_CDC_AIF2_BCLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LOCHNAGAR2_PIN_CDC_AIF2_RXDAT 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LOCHNAGAR2_PIN_CDC_AIF2_LRCLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LOCHNAGAR2_PIN_CDC_AIF2_TXDAT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LOCHNAGAR2_PIN_CDC_AIF3_BCLK 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LOCHNAGAR2_PIN_CDC_AIF3_RXDAT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LOCHNAGAR2_PIN_CDC_AIF3_LRCLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LOCHNAGAR2_PIN_CDC_AIF3_TXDAT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LOCHNAGAR2_PIN_DSP_AIF1_BCLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LOCHNAGAR2_PIN_DSP_AIF1_RXDAT 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LOCHNAGAR2_PIN_DSP_AIF1_LRCLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LOCHNAGAR2_PIN_DSP_AIF1_TXDAT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LOCHNAGAR2_PIN_DSP_AIF2_BCLK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LOCHNAGAR2_PIN_DSP_AIF2_RXDAT 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LOCHNAGAR2_PIN_DSP_AIF2_LRCLK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LOCHNAGAR2_PIN_DSP_AIF2_TXDAT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LOCHNAGAR2_PIN_PSIA1_BCLK 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LOCHNAGAR2_PIN_PSIA1_RXDAT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LOCHNAGAR2_PIN_PSIA1_LRCLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LOCHNAGAR2_PIN_PSIA1_TXDAT 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LOCHNAGAR2_PIN_PSIA2_BCLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LOCHNAGAR2_PIN_PSIA2_RXDAT 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LOCHNAGAR2_PIN_PSIA2_LRCLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LOCHNAGAR2_PIN_PSIA2_TXDAT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LOCHNAGAR2_PIN_GF_AIF3_BCLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LOCHNAGAR2_PIN_GF_AIF3_RXDAT 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LOCHNAGAR2_PIN_GF_AIF3_LRCLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LOCHNAGAR2_PIN_GF_AIF3_TXDAT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LOCHNAGAR2_PIN_GF_AIF4_BCLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LOCHNAGAR2_PIN_GF_AIF4_RXDAT 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LOCHNAGAR2_PIN_GF_AIF4_LRCLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LOCHNAGAR2_PIN_GF_AIF4_TXDAT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LOCHNAGAR2_PIN_GF_AIF1_BCLK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LOCHNAGAR2_PIN_GF_AIF1_RXDAT 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LOCHNAGAR2_PIN_GF_AIF1_LRCLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LOCHNAGAR2_PIN_GF_AIF1_TXDAT 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LOCHNAGAR2_PIN_GF_AIF2_BCLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LOCHNAGAR2_PIN_GF_AIF2_RXDAT 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LOCHNAGAR2_PIN_GF_AIF2_LRCLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LOCHNAGAR2_PIN_GF_AIF2_TXDAT 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LOCHNAGAR2_PIN_DSP_UART1_RX 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define LOCHNAGAR2_PIN_DSP_UART1_TX 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LOCHNAGAR2_PIN_DSP_UART2_RX 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LOCHNAGAR2_PIN_DSP_UART2_TX 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LOCHNAGAR2_PIN_GF_UART2_RX 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LOCHNAGAR2_PIN_GF_UART2_TX 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LOCHNAGAR2_PIN_USB_UART_RX 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LOCHNAGAR2_PIN_CDC_PDMCLK1 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LOCHNAGAR2_PIN_CDC_PDMDAT1 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LOCHNAGAR2_PIN_CDC_PDMCLK2 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LOCHNAGAR2_PIN_CDC_PDMDAT2 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LOCHNAGAR2_PIN_CDC_DMICCLK1 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LOCHNAGAR2_PIN_CDC_DMICDAT1 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LOCHNAGAR2_PIN_CDC_DMICCLK2 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LOCHNAGAR2_PIN_CDC_DMICDAT2 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LOCHNAGAR2_PIN_CDC_DMICCLK3 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LOCHNAGAR2_PIN_CDC_DMICDAT3 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LOCHNAGAR2_PIN_CDC_DMICCLK4 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LOCHNAGAR2_PIN_CDC_DMICDAT4 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LOCHNAGAR2_PIN_DSP_DMICCLK1 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LOCHNAGAR2_PIN_DSP_DMICDAT1 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LOCHNAGAR2_PIN_DSP_DMICCLK2 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LOCHNAGAR2_PIN_DSP_DMICDAT2 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LOCHNAGAR2_PIN_I2C2_SCL 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LOCHNAGAR2_PIN_I2C2_SDA 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LOCHNAGAR2_PIN_I2C3_SCL 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LOCHNAGAR2_PIN_I2C3_SDA 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LOCHNAGAR2_PIN_I2C4_SCL 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LOCHNAGAR2_PIN_I2C4_SDA 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LOCHNAGAR2_PIN_DSP_STANDBY 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LOCHNAGAR2_PIN_CDC_MCLK1 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LOCHNAGAR2_PIN_CDC_MCLK2 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LOCHNAGAR2_PIN_DSP_CLKIN 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LOCHNAGAR2_PIN_PSIA1_MCLK 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LOCHNAGAR2_PIN_PSIA2_MCLK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LOCHNAGAR2_PIN_GF_GPIO1 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LOCHNAGAR2_PIN_GF_GPIO5 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LOCHNAGAR2_PIN_DSP_GPIO20 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LOCHNAGAR2_PIN_NUM_GPIOS 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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