Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * This header provides constants for hisilicon pinctrl bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (c) 2015 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2015 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef _DT_BINDINGS_PINCTRL_HISI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define _DT_BINDINGS_PINCTRL_HISI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* iomg bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MUX_M0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MUX_M1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MUX_M2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MUX_M3		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MUX_M4		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MUX_M5		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MUX_M6		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MUX_M7		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* iocg bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PULL_MASK	(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PULL_DIS	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PULL_UP		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PULL_DOWN	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* drive strength definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRIVE_MASK	(7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRIVE1_02MA	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRIVE1_04MA	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRIVE1_08MA	(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRIVE1_10MA	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRIVE2_02MA	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRIVE2_04MA	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRIVE2_08MA	(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRIVE2_10MA	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRIVE3_04MA	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRIVE3_08MA	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRIVE3_12MA	(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRIVE3_16MA	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DRIVE3_20MA	(4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRIVE3_24MA	(5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DRIVE3_32MA	(6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DRIVE3_40MA	(7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DRIVE4_02MA	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DRIVE4_04MA	(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DRIVE4_08MA	(4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DRIVE4_10MA	(6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* drive strength definition for hi3660 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DRIVE6_MASK	(15 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DRIVE6_04MA	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DRIVE6_12MA	(4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DRIVE6_19MA	(8 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DRIVE6_27MA	(10 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRIVE6_32MA	(15 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DRIVE7_02MA	(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DRIVE7_04MA	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRIVE7_06MA	(2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DRIVE7_08MA	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DRIVE7_10MA	(4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DRIVE7_12MA	(5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DRIVE7_14MA	(6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DRIVE7_16MA	(7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif