Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides constants for DRA pinctrl bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Rajendra Nayak <rnayak@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _DT_BINDINGS_PINCTRL_DRA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DT_BINDINGS_PINCTRL_DRA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* DRA7 mux mode options for each pin. See TRM for options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MUX_MODE0	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MUX_MODE1	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MUX_MODE2	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MUX_MODE3	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MUX_MODE4	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MUX_MODE5	0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MUX_MODE6	0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MUX_MODE7	0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MUX_MODE8	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MUX_MODE9	0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MUX_MODE10	0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MUX_MODE11	0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MUX_MODE12	0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MUX_MODE13	0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MUX_MODE14	0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MUX_MODE15	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Certain pins need virtual mode, but note: they may glitch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MUX_VIRTUAL_MODE0	(MODE_SELECT | (0x0 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MUX_VIRTUAL_MODE1	(MODE_SELECT | (0x1 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MUX_VIRTUAL_MODE2	(MODE_SELECT | (0x2 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MUX_VIRTUAL_MODE3	(MODE_SELECT | (0x3 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MUX_VIRTUAL_MODE4	(MODE_SELECT | (0x4 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MUX_VIRTUAL_MODE5	(MODE_SELECT | (0x5 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MUX_VIRTUAL_MODE6	(MODE_SELECT | (0x6 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MUX_VIRTUAL_MODE7	(MODE_SELECT | (0x7 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MUX_VIRTUAL_MODE8	(MODE_SELECT | (0x8 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MUX_VIRTUAL_MODE9	(MODE_SELECT | (0x9 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MUX_VIRTUAL_MODE10	(MODE_SELECT | (0xa << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MUX_VIRTUAL_MODE11	(MODE_SELECT | (0xb << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MUX_VIRTUAL_MODE12	(MODE_SELECT | (0xc << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MUX_VIRTUAL_MODE13	(MODE_SELECT | (0xd << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MUX_VIRTUAL_MODE14	(MODE_SELECT | (0xe << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MUX_VIRTUAL_MODE15	(MODE_SELECT | (0xf << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MODE_SELECT		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PULL_ENA		(0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PULL_DIS		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PULL_UP			(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define INPUT_EN		(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SLEWCONTROL		(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WAKEUP_EN		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WAKEUP_EVENT		(1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Active pin states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PIN_OUTPUT		(0 | PULL_DIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PIN_OUTPUT_PULLUP	(PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PIN_OUTPUT_PULLDOWN	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PIN_INPUT		(INPUT_EN | PULL_DIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PIN_INPUT_SLEW		(INPUT_EN | SLEWCONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)  * Macro to allow using the absolute physical address instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)  * padconf registers instead of the offset from padconf base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DRA7XX_CORE_IOPAD(pa, val)	(((pa) & 0xffff) - 0x3400) (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* DRA7 IODELAY configuration parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define A_DELAY_PS(val)			((val) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define G_DELAY_PS(val)			((val) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)