Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides constants for most at91 pinctrl bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __DT_BINDINGS_AT91_PINCTRL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __DT_BINDINGS_AT91_PINCTRL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AT91_PINCTRL_NONE		(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AT91_PINCTRL_PULL_UP		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AT91_PINCTRL_MULTI_DRIVE	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AT91_PINCTRL_DEGLITCH		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AT91_PINCTRL_PULL_DOWN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AT91_PINCTRL_DIS_SCHMIT		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AT91_PINCTRL_OUTPUT		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AT91_PINCTRL_OUTPUT_VAL(x)	((x & 0x1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AT91_PINCTRL_SLEWRATE		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AT91_PINCTRL_DEBOUNCE		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AT91_PINCTRL_DEBOUNCE_VAL(x)	(x << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AT91_PINCTRL_PULL_UP_DEGLITCH	(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT		(0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AT91_PINCTRL_DRIVE_STRENGTH_LOW			(0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AT91_PINCTRL_DRIVE_STRENGTH_MED			(0x2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AT91_PINCTRL_DRIVE_STRENGTH_HI			(0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AT91_PINCTRL_SLEWRATE_ENA	(0x0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AT91_PINCTRL_SLEWRATE_DIS	(0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AT91_PIOA	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AT91_PIOB	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AT91_PIOC	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AT91_PIOD	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AT91_PIOE	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AT91_PERIPH_GPIO	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AT91_PERIPH_A		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AT91_PERIPH_B		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AT91_PERIPH_C		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AT91_PERIPH_D		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ATMEL_PIO_DRVSTR_LO	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ATMEL_PIO_DRVSTR_ME	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ATMEL_PIO_DRVSTR_HI	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */