^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This header provides constants specific to AM33XX pinctrl bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_PINCTRL_AM33XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/pinctrl/omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* am33xx specific mux bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #undef PULL_ENA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #undef INPUT_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PULL_DISABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define INPUT_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SLEWCTRL_SLOW (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SLEWCTRL_FAST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* update macro depending on INPUT_EN and PULL_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #undef PIN_OUTPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #undef PIN_OUTPUT_PULLUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #undef PIN_OUTPUT_PULLDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #undef PIN_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #undef PIN_INPUT_PULLUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #undef PIN_INPUT_PULLDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PIN_OUTPUT (PULL_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PIN_OUTPUT_PULLUP (PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PIN_OUTPUT_PULLDOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PIN_INPUT (INPUT_EN | PULL_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PIN_INPUT_PULLDOWN (INPUT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* undef non-existing modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #undef PIN_OFF_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #undef PIN_OFF_OUTPUT_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #undef PIN_OFF_OUTPUT_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #undef PIN_OFF_INPUT_PULLUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #undef PIN_OFF_INPUT_PULLDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #undef PIN_OFF_WAKEUPENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AM335X_PIN_OFFSET_MIN 0x0800U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AM335X_PIN_GPMC_AD0 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AM335X_PIN_GPMC_AD1 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AM335X_PIN_GPMC_AD2 0x808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AM335X_PIN_GPMC_AD3 0x80c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AM335X_PIN_GPMC_AD4 0x810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AM335X_PIN_GPMC_AD5 0x814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AM335X_PIN_GPMC_AD6 0x818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AM335X_PIN_GPMC_AD7 0x81c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AM335X_PIN_GPMC_AD8 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AM335X_PIN_GPMC_AD9 0x824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AM335X_PIN_GPMC_AD10 0x828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AM335X_PIN_GPMC_AD11 0x82c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AM335X_PIN_GPMC_AD12 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AM335X_PIN_GPMC_AD13 0x834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AM335X_PIN_GPMC_AD14 0x838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AM335X_PIN_GPMC_AD15 0x83c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AM335X_PIN_GPMC_A0 0x840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AM335X_PIN_GPMC_A1 0x844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AM335X_PIN_GPMC_A2 0x848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AM335X_PIN_GPMC_A3 0x84c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AM335X_PIN_GPMC_A4 0x850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AM335X_PIN_GPMC_A5 0x854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AM335X_PIN_GPMC_A6 0x858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AM335X_PIN_GPMC_A7 0x85c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AM335X_PIN_GPMC_A8 0x860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AM335X_PIN_GPMC_A9 0x864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AM335X_PIN_GPMC_A10 0x868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AM335X_PIN_GPMC_A11 0x86c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AM335X_PIN_GPMC_WAIT0 0x870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AM335X_PIN_GPMC_WPN 0x874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AM335X_PIN_GPMC_BEN1 0x878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AM335X_PIN_GPMC_CSN0 0x87c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AM335X_PIN_GPMC_CSN1 0x880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AM335X_PIN_GPMC_CSN2 0x884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AM335X_PIN_GPMC_CSN3 0x888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AM335X_PIN_GPMC_CLK 0x88c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AM335X_PIN_GPMC_ADVN_ALE 0x890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AM335X_PIN_GPMC_OEN_REN 0x894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AM335X_PIN_GPMC_WEN 0x898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AM335X_PIN_GPMC_BEN0_CLE 0x89c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AM335X_PIN_LCD_DATA0 0x8a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AM335X_PIN_LCD_DATA1 0x8a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AM335X_PIN_LCD_DATA2 0x8a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AM335X_PIN_LCD_DATA3 0x8ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AM335X_PIN_LCD_DATA4 0x8b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AM335X_PIN_LCD_DATA5 0x8b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AM335X_PIN_LCD_DATA6 0x8b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AM335X_PIN_LCD_DATA7 0x8bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AM335X_PIN_LCD_DATA8 0x8c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AM335X_PIN_LCD_DATA9 0x8c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AM335X_PIN_LCD_DATA10 0x8c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AM335X_PIN_LCD_DATA11 0x8cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AM335X_PIN_LCD_DATA12 0x8d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AM335X_PIN_LCD_DATA13 0x8d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AM335X_PIN_LCD_DATA14 0x8d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AM335X_PIN_LCD_DATA15 0x8dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AM335X_PIN_LCD_VSYNC 0x8e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AM335X_PIN_LCD_HSYNC 0x8e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AM335X_PIN_LCD_PCLK 0x8e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AM335X_PIN_MMC0_DAT3 0x8f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AM335X_PIN_MMC0_DAT2 0x8f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AM335X_PIN_MMC0_DAT1 0x8f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AM335X_PIN_MMC0_DAT0 0x8fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AM335X_PIN_MMC0_CLK 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AM335X_PIN_MMC0_CMD 0x904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AM335X_PIN_MII1_COL 0x908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AM335X_PIN_MII1_CRS 0x90c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AM335X_PIN_MII1_RX_ER 0x910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AM335X_PIN_MII1_TX_EN 0x914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AM335X_PIN_MII1_RX_DV 0x918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AM335X_PIN_MII1_TXD3 0x91c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AM335X_PIN_MII1_TXD2 0x920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AM335X_PIN_MII1_TXD1 0x924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AM335X_PIN_MII1_TXD0 0x928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AM335X_PIN_MII1_TX_CLK 0x92c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AM335X_PIN_MII1_RX_CLK 0x930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AM335X_PIN_MII1_RXD3 0x934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AM335X_PIN_MII1_RXD2 0x938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AM335X_PIN_MII1_RXD1 0x93c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AM335X_PIN_MII1_RXD0 0x940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AM335X_PIN_RMII1_REF_CLK 0x944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AM335X_PIN_MDIO 0x948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AM335X_PIN_MDC 0x94c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AM335X_PIN_SPI0_SCLK 0x950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AM335X_PIN_SPI0_D0 0x954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AM335X_PIN_SPI0_D1 0x958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AM335X_PIN_SPI0_CS0 0x95c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AM335X_PIN_SPI0_CS1 0x960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AM335X_PIN_UART0_CTSN 0x968
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AM335X_PIN_UART0_RTSN 0x96c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AM335X_PIN_UART0_RXD 0x970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AM335X_PIN_UART0_TXD 0x974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AM335X_PIN_UART1_CTSN 0x978
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AM335X_PIN_UART1_RTSN 0x97c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AM335X_PIN_UART1_RXD 0x980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AM335X_PIN_UART1_TXD 0x984
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AM335X_PIN_I2C0_SDA 0x988
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AM335X_PIN_I2C0_SCL 0x98c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AM335X_PIN_MCASP0_ACLKX 0x990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AM335X_PIN_MCASP0_FSX 0x994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AM335X_PIN_MCASP0_AXR0 0x998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AM335X_PIN_MCASP0_AHCLKR 0x99c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AM335X_PIN_MCASP0_ACLKR 0x9a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AM335X_PIN_MCASP0_FSR 0x9a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AM335X_PIN_MCASP0_AXR1 0x9a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AM335X_PIN_MCASP0_AHCLKX 0x9ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AM335X_PIN_WARMRSTN 0x9b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AM335X_PIN_NNMI 0x9c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AM335X_PIN_TMS 0x9d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AM335X_PIN_TDI 0x9d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AM335X_PIN_TDO 0x9d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AM335X_PIN_TCK 0x9dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AM335X_PIN_TRSTN 0x9e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AM335X_PIN_EMU0 0x9e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AM335X_PIN_EMU1 0x9e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AM335X_PIN_RTC_PWRONRSTN 0x9f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AM335X_PIN_PMIC_POWER_EN 0x9fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AM335X_PIN_EXT_WAKEUP 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AM335X_PIN_USB0_DRVVBUS 0xa1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AM335X_PIN_USB1_DRVVBUS 0xa34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AM335X_PIN_OFFSET_MAX 0x0a34U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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