Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Device Tree constants for the Texas Instruments DP83869 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Dan Murphy <dmurphy@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright:   (C) 2019 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _DT_BINDINGS_TI_DP83869_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _DT_BINDINGS_TI_DP83869_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* PHY CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* IO_MUX_CFG - Clock output selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DP83869_CLK_O_SEL_CHN_A_RCLK		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DP83869_CLK_O_SEL_CHN_B_RCLK		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DP83869_CLK_O_SEL_CHN_C_RCLK		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DP83869_CLK_O_SEL_CHN_D_RCLK		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5	0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5	0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5	0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DP83869_CLK_O_SEL_CHN_A_TCLK		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DP83869_CLK_O_SEL_CHN_B_TCLK		0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DP83869_CLK_O_SEL_CHN_C_TCLK		0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DP83869_CLK_O_SEL_CHN_D_TCLK		0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DP83869_CLK_O_SEL_REF_CLK		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DP83869_RGMII_COPPER_ETHERNET		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DP83869_RGMII_1000_BASE			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DP83869_RGMII_100_BASE			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DP83869_RGMII_SGMII_BRIDGE		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DP83869_1000M_MEDIA_CONVERT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DP83869_100M_MEDIA_CONVERT		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DP83869_SGMII_COPPER_ETHERNET		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif