^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This header provides constants for SERDES MUX for TI SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_MUX_TI_SERDES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_MUX_TI_SERDES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* J721E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define J721E_SERDES0_LANE1_USB3_0 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define J721E_SERDES1_LANE1_USB3_1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define J721E_SERDES2_LANE0_IP1_UNUSED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define J721E_SERDES2_LANE1_IP1_UNUSED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define J721E_SERDES2_LANE1_USB3_1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define J721E_SERDES3_LANE0_IP1_UNUSED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define J721E_SERDES3_LANE1_IP1_UNUSED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define J721E_SERDES3_LANE1_USB3_0 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define J721E_SERDES4_LANE0_EDP_LANE0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define J721E_SERDES4_LANE1_EDP_LANE1 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define J721E_SERDES4_LANE2_EDP_LANE2 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define J721E_SERDES4_LANE2_IP2_UNUSED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define J721E_SERDES4_LANE2_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define J721E_SERDES4_LANE3_EDP_LANE3 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define J721E_SERDES4_LANE3_IP2_UNUSED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* J7200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define J7200_SERDES0_LANE3_USB 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif /* _DT_BINDINGS_MUX_TI_SERDES */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags