^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This header provides constants for the STM32H7 RCC IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define _DT_BINDINGS_MFD_STM32H7_RCC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* AHB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define STM32H7_RCC_AHB3_MDMA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define STM32H7_RCC_AHB3_DMA2D 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define STM32H7_RCC_AHB3_JPGDEC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define STM32H7_RCC_AHB3_FMC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define STM32H7_RCC_AHB3_QUADSPI 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define STM32H7_RCC_AHB3_SDMMC1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define STM32H7_RCC_AHB3_CPU 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* AHB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STM32H7_RCC_AHB1_DMA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STM32H7_RCC_AHB1_DMA2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STM32H7_RCC_AHB1_ADC12 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STM32H7_RCC_AHB1_ART 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STM32H7_RCC_AHB1_ETH1MAC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STM32H7_RCC_AHB1_USB1OTG 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STM32H7_RCC_AHB1_USB2OTG 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* AHB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STM32H7_RCC_AHB2_CAMITF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STM32H7_RCC_AHB2_CRYPT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STM32H7_RCC_AHB2_HASH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STM32H7_RCC_AHB2_RNG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STM32H7_RCC_AHB2_SDMMC2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* AHB4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STM32H7_RCC_AHB4_GPIOA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STM32H7_RCC_AHB4_GPIOB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STM32H7_RCC_AHB4_GPIOC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STM32H7_RCC_AHB4_GPIOD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STM32H7_RCC_AHB4_GPIOE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STM32H7_RCC_AHB4_GPIOF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STM32H7_RCC_AHB4_GPIOG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STM32H7_RCC_AHB4_GPIOH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STM32H7_RCC_AHB4_GPIOI 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STM32H7_RCC_AHB4_GPIOJ 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STM32H7_RCC_AHB4_GPIOK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STM32H7_RCC_AHB4_CRC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STM32H7_RCC_AHB4_BDMA 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STM32H7_RCC_AHB4_ADC3 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STM32H7_RCC_AHB4_HSEM 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* APB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STM32H7_RCC_APB3_LTDC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STM32H7_RCC_APB3_DSI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* APB1L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STM32H7_RCC_APB1L_TIM2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STM32H7_RCC_APB1L_TIM3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STM32H7_RCC_APB1L_TIM4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STM32H7_RCC_APB1L_TIM5 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define STM32H7_RCC_APB1L_TIM6 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define STM32H7_RCC_APB1L_TIM7 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define STM32H7_RCC_APB1L_TIM12 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STM32H7_RCC_APB1L_TIM13 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define STM32H7_RCC_APB1L_TIM14 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STM32H7_RCC_APB1L_LPTIM1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define STM32H7_RCC_APB1L_SPI2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STM32H7_RCC_APB1L_SPI3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STM32H7_RCC_APB1L_SPDIF_RX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define STM32H7_RCC_APB1L_USART2 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STM32H7_RCC_APB1L_USART3 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STM32H7_RCC_APB1L_UART4 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define STM32H7_RCC_APB1L_UART5 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define STM32H7_RCC_APB1L_I2C1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define STM32H7_RCC_APB1L_I2C2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define STM32H7_RCC_APB1L_I2C3 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define STM32H7_RCC_APB1L_HDMICEC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define STM32H7_RCC_APB1L_DAC12 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define STM32H7_RCC_APB1L_USART7 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define STM32H7_RCC_APB1L_USART8 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* APB1H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STM32H7_RCC_APB1H_CRS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STM32H7_RCC_APB1H_SWP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define STM32H7_RCC_APB1H_OPAMP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define STM32H7_RCC_APB1H_MDIOS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define STM32H7_RCC_APB1H_FDCAN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* APB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STM32H7_RCC_APB2_TIM1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define STM32H7_RCC_APB2_TIM8 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define STM32H7_RCC_APB2_USART1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define STM32H7_RCC_APB2_USART6 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define STM32H7_RCC_APB2_SPI1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STM32H7_RCC_APB2_SPI4 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define STM32H7_RCC_APB2_TIM15 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define STM32H7_RCC_APB2_TIM16 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define STM32H7_RCC_APB2_TIM17 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define STM32H7_RCC_APB2_SPI5 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define STM32H7_RCC_APB2_SAI1 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define STM32H7_RCC_APB2_SAI2 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define STM32H7_RCC_APB2_SAI3 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define STM32H7_RCC_APB2_DFSDM1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define STM32H7_RCC_APB2_HRTIM 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* APB4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define STM32H7_RCC_APB4_SYSCFG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define STM32H7_RCC_APB4_LPUART1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define STM32H7_RCC_APB4_SPI6 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define STM32H7_RCC_APB4_I2C4 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define STM32H7_RCC_APB4_LPTIM2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define STM32H7_RCC_APB4_LPTIM3 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define STM32H7_RCC_APB4_LPTIM4 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define STM32H7_RCC_APB4_LPTIM5 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define STM32H7_RCC_APB4_COMP12 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define STM32H7_RCC_APB4_VREF 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define STM32H7_RCC_APB4_SAI4 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define STM32H7_RCC_APB4_TMPSENS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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