^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This header provides constants for the STM32F7 RCC IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_MFD_STM32F7_RCC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* AHB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define STM32F7_RCC_AHB1_GPIOA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define STM32F7_RCC_AHB1_GPIOB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define STM32F7_RCC_AHB1_GPIOC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define STM32F7_RCC_AHB1_GPIOD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define STM32F7_RCC_AHB1_GPIOE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define STM32F7_RCC_AHB1_GPIOF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define STM32F7_RCC_AHB1_GPIOG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STM32F7_RCC_AHB1_GPIOH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STM32F7_RCC_AHB1_GPIOI 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STM32F7_RCC_AHB1_GPIOJ 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STM32F7_RCC_AHB1_GPIOK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STM32F7_RCC_AHB1_CRC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STM32F7_RCC_AHB1_BKPSRAM 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STM32F7_RCC_AHB1_DTCMRAM 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STM32F7_RCC_AHB1_DMA1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STM32F7_RCC_AHB1_DMA2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STM32F7_RCC_AHB1_DMA2D 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STM32F7_RCC_AHB1_ETHMAC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STM32F7_RCC_AHB1_ETHMACTX 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STM32F7_RCC_AHB1_ETHMACRX 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STM32FF_RCC_AHB1_ETHMACPTP 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STM32F7_RCC_AHB1_OTGHS 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STM32F7_RCC_AHB1_OTGHSULPI 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* AHB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STM32F7_RCC_AHB2_DCMI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STM32F7_RCC_AHB2_CRYP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STM32F7_RCC_AHB2_HASH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STM32F7_RCC_AHB2_RNG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STM32F7_RCC_AHB2_OTGFS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* AHB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STM32F7_RCC_AHB3_FMC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STM32F7_RCC_AHB3_QSPI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* APB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STM32F7_RCC_APB1_TIM2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STM32F7_RCC_APB1_TIM3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STM32F7_RCC_APB1_TIM4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STM32F7_RCC_APB1_TIM5 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STM32F7_RCC_APB1_TIM6 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STM32F7_RCC_APB1_TIM7 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STM32F7_RCC_APB1_TIM12 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STM32F7_RCC_APB1_TIM13 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STM32F7_RCC_APB1_TIM14 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STM32F7_RCC_APB1_LPTIM1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STM32F7_RCC_APB1_WWDG 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STM32F7_RCC_APB1_SPI2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STM32F7_RCC_APB1_SPI3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define STM32F7_RCC_APB1_SPDIFRX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define STM32F7_RCC_APB1_UART2 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define STM32F7_RCC_APB1_UART3 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STM32F7_RCC_APB1_UART4 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define STM32F7_RCC_APB1_UART5 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STM32F7_RCC_APB1_I2C1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define STM32F7_RCC_APB1_I2C2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STM32F7_RCC_APB1_I2C3 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STM32F7_RCC_APB1_I2C4 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define STM32F7_RCC_APB1_CAN1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STM32F7_RCC_APB1_CAN2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STM32F7_RCC_APB1_CEC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define STM32F7_RCC_APB1_PWR 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define STM32F7_RCC_APB1_DAC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define STM32F7_RCC_APB1_UART7 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define STM32F7_RCC_APB1_UART8 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* APB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define STM32F7_RCC_APB2_TIM1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define STM32F7_RCC_APB2_TIM8 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define STM32F7_RCC_APB2_USART1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STM32F7_RCC_APB2_USART6 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STM32F7_RCC_APB2_SDMMC2 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define STM32F7_RCC_APB2_ADC1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define STM32F7_RCC_APB2_ADC2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define STM32F7_RCC_APB2_ADC3 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STM32F7_RCC_APB2_SDMMC1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define STM32F7_RCC_APB2_SPI1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define STM32F7_RCC_APB2_SPI4 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STM32F7_RCC_APB2_SYSCFG 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STM32F7_RCC_APB2_TIM9 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define STM32F7_RCC_APB2_TIM10 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define STM32F7_RCC_APB2_TIM11 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define STM32F7_RCC_APB2_SPI5 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define STM32F7_RCC_APB2_SPI6 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STM32F7_RCC_APB2_SAI1 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define STM32F7_RCC_APB2_SAI2 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define STM32F7_RCC_APB2_LTDC 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */
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Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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