Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides macros for MAXIM MAX77620 device bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2016, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _DT_BINDINGS_MFD_MAX77620_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DT_BINDINGS_MFD_MAX77620_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* MAX77620 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MAX77620_IRQ_TOP_GLBL		0 /* Low-Battery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MAX77620_IRQ_TOP_SD		1 /* SD power fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MAX77620_IRQ_TOP_LDO		2 /* LDO power fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MAX77620_IRQ_TOP_GPIO		3 /* GPIO internal int to MAX77620 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MAX77620_IRQ_TOP_RTC		4 /* RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MAX77620_IRQ_TOP_32K		5 /* 32kHz oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MAX77620_IRQ_TOP_ONOFF		6 /* ON/OFF oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MAX77620_IRQ_LBT_MBATLOW	7 /* Thermal alarm status, > 120C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAX77620_IRQ_LBT_TJALRM1	8 /* Thermal alarm status, > 120C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MAX77620_IRQ_LBT_TJALRM2	9 /* Thermal alarm status, > 140C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* FPS event source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX77620_FPS_EVENT_SRC_EN0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAX77620_FPS_EVENT_SRC_EN1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MAX77620_FPS_EVENT_SRC_SW		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Device state when FPS event LOW  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX77620_FPS_INACTIVE_STATE_SLEEP	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MAX77620_FPS_INACTIVE_STATE_LOW_POWER	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* FPS source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX77620_FPS_SRC_0			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX77620_FPS_SRC_1			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX77620_FPS_SRC_2			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MAX77620_FPS_SRC_NONE			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX77620_FPS_SRC_DEF			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif