Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides constants for the PRCMU bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_MFD_PRCMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_MFD_PRCMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * Clock identifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ARMCLK			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PRCMU_ACLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PRCMU_SVAMMCSPCLK 	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PRCMU_SDMMCHCLK 	2  /* DBx540 only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PRCMU_SIACLK 		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PRCMU_SIAMMDSPCLK 	3  /* DBx540 only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PRCMU_SGACLK 		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PRCMU_UARTCLK 		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PRCMU_MSP02CLK 		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PRCMU_MSP1CLK 		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PRCMU_I2CCLK 		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PRCMU_SDMMCCLK 		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PRCMU_SLIMCLK 		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PRCMU_CAMCLK 		10 /* DBx540 only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PRCMU_PER1CLK 		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PRCMU_PER2CLK 		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PRCMU_PER3CLK 		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PRCMU_PER5CLK 		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PRCMU_PER6CLK 		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PRCMU_PER7CLK 		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PRCMU_LCDCLK 		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PRCMU_BMLCLK 		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PRCMU_HSITXCLK 		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PRCMU_HSIRXCLK 		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PRCMU_HDMICLK		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PRCMU_APEATCLK 		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PRCMU_APETRACECLK 	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PRCMU_MCDECLK  	 	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PRCMU_IPI2CCLK  	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PRCMU_DSIALTCLK  	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PRCMU_DMACLK  	 	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PRCMU_B2R2CLK  	 	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PRCMU_TVCLK  	 	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPARE_UNIPROCLK  	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PRCMU_SSPCLK  	 	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PRCMU_RNGCLK  	 	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PRCMU_UICCCLK  	 	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PRCMU_G1CLK             34 /* DBx540 only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PRCMU_HVACLK            35 /* DBx540 only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PRCMU_SPARE1CLK	 	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PRCMU_SPARE2CLK	 	37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PRCMU_NUM_REG_CLOCKS  	38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PRCMU_RTCCLK  	 	PRCMU_NUM_REG_CLOCKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PRCMU_SYSCLK  	 	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PRCMU_CDCLK  	 	40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PRCMU_TIMCLK  	 	41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PRCMU_PLLSOC0  	 	42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PRCMU_PLLSOC1  	 	43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PRCMU_ARMSS  	 	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PRCMU_PLLDDR  	 	45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* DSI Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PRCMU_PLLDSI  	 	46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PRCMU_DSI0CLK 	  	47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PRCMU_DSI1CLK  	 	48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PRCMU_DSI0ESCCLK  	49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PRCMU_DSI1ESCCLK  	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PRCMU_DSI2ESCCLK  	51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* LCD DSI PLL - Ux540 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PRCMU_PLLDSI_LCD        52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PRCMU_DSI0CLK_LCD       53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PRCMU_DSI1CLK_LCD       54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PRCMU_DSI0ESCCLK_LCD    55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PRCMU_DSI1ESCCLK_LCD    56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PRCMU_DSI2ESCCLK_LCD    57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PRCMU_NUM_CLKS  	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif