Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides macros for ams AS3722 device bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2013, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __DT_BINDINGS_AS3722_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __DT_BINDINGS_AS3722_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* External control pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AS3722_EXT_CONTROL_PIN_ENABLE1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AS3722_EXT_CONTROL_PIN_ENABLE2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AS3722_EXT_CONTROL_PIN_ENABLE3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Interrupt numbers for AS3722 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AS3722_IRQ_LID			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AS3722_IRQ_ACOK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AS3722_IRQ_ENABLE1		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AS3722_IRQ_OCCUR_ALARM_SD0	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AS3722_IRQ_ONKEY_LONG_PRESS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AS3722_IRQ_ONKEY		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AS3722_IRQ_OVTMP		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AS3722_IRQ_LOWBAT		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AS3722_IRQ_SD0_LV		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AS3722_IRQ_SD1_LV		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AS3722_IRQ_SD2_LV		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AS3722_IRQ_PWM1_OV_PROT		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AS3722_IRQ_PWM2_OV_PROT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AS3722_IRQ_ENABLE2		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AS3722_IRQ_SD6_LV		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AS3722_IRQ_RTC_REP		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AS3722_IRQ_RTC_ALARM		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AS3722_IRQ_GPIO1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AS3722_IRQ_GPIO2		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AS3722_IRQ_GPIO3		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AS3722_IRQ_GPIO4		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AS3722_IRQ_GPIO5		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AS3722_IRQ_WATCHDOG		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AS3722_IRQ_ENABLE3		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AS3722_IRQ_TEMP_SD0_SHUTDOWN	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AS3722_IRQ_TEMP_SD1_SHUTDOWN	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AS3722_IRQ_TEMP_SD2_SHUTDOWN	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AS3722_IRQ_TEMP_SD0_ALARM	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AS3722_IRQ_TEMP_SD1_ALARM	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AS3722_IRQ_TEMP_SD6_ALARM	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AS3722_IRQ_OCCUR_ALARM_SD6	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AS3722_IRQ_ADC			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif /* __DT_BINDINGS_AS3722_H__ */