Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define DT_BINDINGS_MEMORY_TEGRA30_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define TEGRA_SWGROUP_PTC	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define TEGRA_SWGROUP_DC	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define TEGRA_SWGROUP_DCB	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define TEGRA_SWGROUP_EPP	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define TEGRA_SWGROUP_G2	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TEGRA_SWGROUP_MPE	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TEGRA_SWGROUP_VI	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TEGRA_SWGROUP_AFI	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA_SWGROUP_AVPC	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA_SWGROUP_NV	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA_SWGROUP_NV2	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA_SWGROUP_HDA	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA_SWGROUP_HC	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA_SWGROUP_PPCS	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA_SWGROUP_SATA	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA_SWGROUP_VDE	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA_SWGROUP_MPCORELP	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA_SWGROUP_MPCORE	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA_SWGROUP_ISP	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA30_MC_RESET_AFI		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA30_MC_RESET_AVPC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA30_MC_RESET_DC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA30_MC_RESET_DCB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA30_MC_RESET_EPP		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA30_MC_RESET_2D		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA30_MC_RESET_HC		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA30_MC_RESET_HDA		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA30_MC_RESET_ISP		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA30_MC_RESET_MPCORE		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA30_MC_RESET_MPCORELP	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA30_MC_RESET_MPE		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA30_MC_RESET_3D		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA30_MC_RESET_3D2		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA30_MC_RESET_PPCS		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA30_MC_RESET_SATA		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA30_MC_RESET_VDE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA30_MC_RESET_VI		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif