Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) #ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #define DT_BINDINGS_MEMORY_TEGRA194_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /* special clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #define TEGRA194_SID_INVALID		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define TEGRA194_SID_PASSTHROUGH	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) /* host1x clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define TEGRA194_SID_HOST1X		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define TEGRA194_SID_CSI		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define TEGRA194_SID_VIC		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define TEGRA194_SID_VI			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define TEGRA194_SID_ISP		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define TEGRA194_SID_NVDEC		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define TEGRA194_SID_NVENC		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define TEGRA194_SID_NVJPG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define TEGRA194_SID_NVDISPLAY		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TEGRA194_SID_TSEC		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TEGRA194_SID_TSECB		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TEGRA194_SID_SE			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TEGRA194_SID_SE1		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TEGRA194_SID_SE2		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TEGRA194_SID_SE3		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* GPU clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TEGRA194_SID_GPU		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* other SoC clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TEGRA194_SID_AFI		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TEGRA194_SID_HDA		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TEGRA194_SID_ETR		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TEGRA194_SID_EQOS		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TEGRA194_SID_UFSHC		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TEGRA194_SID_AON		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TEGRA194_SID_SDMMC4		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TEGRA194_SID_SDMMC3		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TEGRA194_SID_SDMMC2		0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TEGRA194_SID_SDMMC1		0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TEGRA194_SID_XUSB_HOST		0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TEGRA194_SID_XUSB_DEV		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TEGRA194_SID_SATA		0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TEGRA194_SID_APE		0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TEGRA194_SID_SCE		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* GPC DMA clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TEGRA194_SID_GPCDMA_0		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TEGRA194_SID_GPCDMA_1		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TEGRA194_SID_GPCDMA_2		0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TEGRA194_SID_GPCDMA_3		0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TEGRA194_SID_GPCDMA_4		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TEGRA194_SID_GPCDMA_5		0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TEGRA194_SID_GPCDMA_6		0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TEGRA194_SID_GPCDMA_7		0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* APE DMA clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TEGRA194_SID_APE_1		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TEGRA194_SID_APE_2		0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* camera RTCPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TEGRA194_SID_RCE		0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* camera RTCPU on host1x address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define TEGRA194_SID_RCE_1X		0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* APE DMA clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TEGRA194_SID_APE_3		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* camera RTCPU running on APE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TEGRA194_SID_APE_CAM		0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TEGRA194_SID_APE_CAM_1X		0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define TEGRA194_SID_RCE_RM		0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TEGRA194_SID_VI_FALCON		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define TEGRA194_SID_ISP_FALCON		0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * The BPMP has its SID value hardcoded in the firmware. Changing it requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * considerable effort.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define TEGRA194_SID_BPMP		0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* for SMMU tests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define TEGRA194_SID_SMMU_TEST		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* host1x virtualization channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define TEGRA194_SID_HOST1X_CTX0	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TEGRA194_SID_HOST1X_CTX1	0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define TEGRA194_SID_HOST1X_CTX2	0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TEGRA194_SID_HOST1X_CTX3	0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define TEGRA194_SID_HOST1X_CTX4	0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TEGRA194_SID_HOST1X_CTX5	0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TEGRA194_SID_HOST1X_CTX6	0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TEGRA194_SID_HOST1X_CTX7	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /* host1x command buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TEGRA194_SID_HOST1X_VM0		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TEGRA194_SID_HOST1X_VM1		0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TEGRA194_SID_HOST1X_VM2		0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define TEGRA194_SID_HOST1X_VM3		0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA194_SID_HOST1X_VM4		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA194_SID_HOST1X_VM5		0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA194_SID_HOST1X_VM6		0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA194_SID_HOST1X_VM7		0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* SE data buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA194_SID_SE_VM0		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA194_SID_SE_VM1		0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA194_SID_SE_VM2		0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA194_SID_SE_VM3		0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA194_SID_SE_VM4		0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA194_SID_SE_VM5		0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA194_SID_SE_VM6		0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA194_SID_SE_VM7		0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA194_SID_MIU		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA194_SID_NVDLA0		0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA194_SID_NVDLA1		0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA194_SID_PVA0		0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA194_SID_PVA1		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA194_SID_NVENC1		0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA194_SID_PCIE0		0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA194_SID_PCIE1		0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA194_SID_PCIE2		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA194_SID_PCIE3		0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA194_SID_PCIE4		0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA194_SID_PCIE5		0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA194_SID_NVDEC1		0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA194_SID_XUSB_VF0		0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA194_SID_XUSB_VF1		0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA194_SID_XUSB_VF2		0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA194_SID_XUSB_VF3		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA194_SID_RCE_VM3		0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA194_SID_VI_VM2		0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA194_SID_VI_VM3		0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA194_SID_RCE_SERVER		0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * memory client IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA194_MEMORY_CLIENT_PTCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* MSS internal memqual MIU7 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA194_MEMORY_CLIENT_MIU7R 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* MSS internal memqual MIU7 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA194_MEMORY_CLIENT_MIU7W 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* High-definition audio (HDA) read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA194_MEMORY_CLIENT_HDAR 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Host channel data read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* SATA read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TEGRA194_MEMORY_CLIENT_SATAR 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Reads from Cortex-A9 4 CPU cores via the L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TEGRA194_MEMORY_CLIENT_MPCORER 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* High-definition audio (HDA) write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TEGRA194_MEMORY_CLIENT_HDAW 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Writes from Cortex-A9 4 CPU cores via the L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* SATA write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TEGRA194_MEMORY_CLIENT_SATAW 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* ISP read client for Crossbar A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA194_MEMORY_CLIENT_ISPRA 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* ISP read client 1 for Crossbar A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* ISP Write client for Crossbar A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA194_MEMORY_CLIENT_ISPWA 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* ISP Write client Crossbar B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA194_MEMORY_CLIENT_ISPWB 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* XUSB_HOST read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* XUSB_HOST write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* XUSB read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* XUSB_DEV write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* sdmmca memory read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* sdmmc memory read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* sdmmcd memory read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* sdmmca memory write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* sdmmc memory write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* sdmmcd memory write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* VI Write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEGRA194_MEMORY_CLIENT_VIW 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Audio Processing (APE) engine read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TEGRA194_MEMORY_CLIENT_APER 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Audio Processing (APE) engine write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA194_MEMORY_CLIENT_APEW 0x7b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* ETR read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TEGRA194_MEMORY_CLIENT_ETRR 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* ETR write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TEGRA194_MEMORY_CLIENT_ETRW 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* AXI Switch read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TEGRA194_MEMORY_CLIENT_AXISR 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* AXI Switch write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TEGRA194_MEMORY_CLIENT_AXISW 0x8d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* EQOS read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* EQOS write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* UFSHC read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* UFSHC write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* NVDISPLAY read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* BPMP read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TEGRA194_MEMORY_CLIENT_BPMPR 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* BPMP write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TEGRA194_MEMORY_CLIENT_BPMPW 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* BPMPDMA read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* BPMPDMA write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* AON read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TEGRA194_MEMORY_CLIENT_AONR 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* AON write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TEGRA194_MEMORY_CLIENT_AONW 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* AONDMA read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* AONDMA write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* SCE read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA194_MEMORY_CLIENT_SCER 0x9b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* SCE write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA194_MEMORY_CLIENT_SCEW 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* SCEDMA read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* SCEDMA write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* APEDMA read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* APEDMA write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* NVDISPLAY read client instance 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* MSS internal memqual MIU0 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* MSS internal memqual MIU0 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* MSS internal memqual MIU1 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* MSS internal memqual MIU1 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* MSS internal memqual MIU2 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TEGRA194_MEMORY_CLIENT_MIU2R 0xae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* MSS internal memqual MIU2 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* MSS internal memqual MIU3 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* MSS internal memqual MIU3 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* MSS internal memqual MIU4 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* MSS internal memqual MIU4 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TEGRA194_MEMORY_CLIENT_NVL2R 0xba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* VI FLACON read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* VIFAL write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* DLA0ARDA read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* DLA0 Falcon read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* DLA0 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* DLA0 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* DLA1ARDA read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* DLA1 Falcon read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* DLA1 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* DLA1 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* PVA0RDA read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* PVA0RDB read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* PVA0RDC read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* PVA0WRA write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* PVA0WRB write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* PVA0WRC write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* PVA1RDA read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* PVA1RDB read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* PVA1RDC read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* PVA1WRA write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* PVA1WRB write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* PVA1WRC write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* RCE read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TEGRA194_MEMORY_CLIENT_RCER 0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* RCE write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TEGRA194_MEMORY_CLIENT_RCEW 0xd3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* RCEDMA read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* RCEDMA write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* PCIE0 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* PCIE0 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* PCIE1 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* PCIE1 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* PCIE2 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* PCIE2 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* PCIE3 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* PCIE3 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* PCIE4 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* PCIE4 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* PCIE5 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* PCIE5 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* ISP read client 1 for Crossbar A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* DLA0ARDA1 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* DLA1ARDA1 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* PVA0RDA1 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* PVA0RDB1 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* PVA1RDA1 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* PVA1RDB1 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* PCIE5r1 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* ISP read client for Crossbar A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* PCIE0 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* MSS internal memqual MIU5 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* MSS internal memqual MIU5 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* MSS internal memqual MIU6 read clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* MSS internal memqual MIU6 write clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define TEGRA194_MEMORY_CLIENT_MIU6W 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #endif