Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) #ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #define DT_BINDINGS_MEMORY_TEGRA186_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /* special clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #define TEGRA186_SID_INVALID		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define TEGRA186_SID_PASSTHROUGH	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) /* host1x clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define TEGRA186_SID_HOST1X		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define TEGRA186_SID_CSI		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define TEGRA186_SID_VIC		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define TEGRA186_SID_VI			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define TEGRA186_SID_ISP		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define TEGRA186_SID_NVDEC		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define TEGRA186_SID_NVENC		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define TEGRA186_SID_NVJPG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define TEGRA186_SID_NVDISPLAY		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TEGRA186_SID_TSEC		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TEGRA186_SID_TSECB		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TEGRA186_SID_SE			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TEGRA186_SID_SE1		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TEGRA186_SID_SE2		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TEGRA186_SID_SE3		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* GPU clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TEGRA186_SID_GPU		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* other SoC clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TEGRA186_SID_AFI		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TEGRA186_SID_HDA		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TEGRA186_SID_ETR		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TEGRA186_SID_EQOS		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TEGRA186_SID_UFSHC		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TEGRA186_SID_AON		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TEGRA186_SID_SDMMC4		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TEGRA186_SID_SDMMC3		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TEGRA186_SID_SDMMC2		0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TEGRA186_SID_SDMMC1		0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TEGRA186_SID_XUSB_HOST		0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TEGRA186_SID_XUSB_DEV		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TEGRA186_SID_SATA		0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TEGRA186_SID_APE		0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TEGRA186_SID_SCE		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* GPC DMA clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TEGRA186_SID_GPCDMA_0		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TEGRA186_SID_GPCDMA_1		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TEGRA186_SID_GPCDMA_2		0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TEGRA186_SID_GPCDMA_3		0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TEGRA186_SID_GPCDMA_4		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TEGRA186_SID_GPCDMA_5		0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TEGRA186_SID_GPCDMA_6		0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TEGRA186_SID_GPCDMA_7		0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* APE DMA clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TEGRA186_SID_APE_1		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TEGRA186_SID_APE_2		0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* camera RTCPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TEGRA186_SID_RCE		0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* camera RTCPU on host1x address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define TEGRA186_SID_RCE_1X		0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* APE DMA clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TEGRA186_SID_APE_3		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* camera RTCPU running on APE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TEGRA186_SID_APE_CAM		0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TEGRA186_SID_APE_CAM_1X		0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * The BPMP has its SID value hardcoded in the firmware. Changing it requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * considerable effort.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define TEGRA186_SID_BPMP		0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* for SMMU tests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TEGRA186_SID_SMMU_TEST		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* host1x virtualization channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define TEGRA186_SID_HOST1X_CTX0	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define TEGRA186_SID_HOST1X_CTX1	0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define TEGRA186_SID_HOST1X_CTX2	0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define TEGRA186_SID_HOST1X_CTX3	0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define TEGRA186_SID_HOST1X_CTX4	0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TEGRA186_SID_HOST1X_CTX5	0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define TEGRA186_SID_HOST1X_CTX6	0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TEGRA186_SID_HOST1X_CTX7	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* host1x command buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TEGRA186_SID_HOST1X_VM0		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TEGRA186_SID_HOST1X_VM1		0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TEGRA186_SID_HOST1X_VM2		0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TEGRA186_SID_HOST1X_VM3		0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TEGRA186_SID_HOST1X_VM4		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TEGRA186_SID_HOST1X_VM5		0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TEGRA186_SID_HOST1X_VM6		0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define TEGRA186_SID_HOST1X_VM7		0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* SE data buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA186_SID_SE_VM0		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA186_SID_SE_VM1		0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA186_SID_SE_VM2		0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA186_SID_SE_VM3		0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA186_SID_SE_VM4		0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA186_SID_SE_VM5		0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA186_SID_SE_VM6		0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA186_SID_SE_VM7		0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * memory client IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA186_MEMORY_CLIENT_PTCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* PCIE reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA186_MEMORY_CLIENT_AFIR 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* High-definition audio (HDA) reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA186_MEMORY_CLIENT_HDAR 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Host channel data reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* SATA reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA186_MEMORY_CLIENT_SATAR 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Reads from Cortex-A9 4 CPU cores via the L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA186_MEMORY_CLIENT_MPCORER 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* PCIE writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA186_MEMORY_CLIENT_AFIW 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* High-definition audio (HDA) writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA186_MEMORY_CLIENT_HDAW 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Writes from Cortex-A9 4 CPU cores via the L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* SATA writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA186_MEMORY_CLIENT_SATAW 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* ISP Read client for Crossbar A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA186_MEMORY_CLIENT_ISPRA 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* ISP Write client for Crossbar A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA186_MEMORY_CLIENT_ISPWA 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* ISP Write client Crossbar B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA186_MEMORY_CLIENT_ISPWB 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* XUSB reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* XUSB_HOST writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* XUSB reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* XUSB_DEV writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* TSEC Memory Return Data Client Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* TSEC Memory Write Client Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* 3D, ltcx reads instance 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* 3D, ltcx writes instance 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* sdmmca memory read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* sdmmcbmemory read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* sdmmc memory read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* sdmmcd memory read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* sdmmca memory write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* sdmmcb memory write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* sdmmc memory write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* sdmmcd memory write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* VI Write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TEGRA186_MEMORY_CLIENT_VIW 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Audio Processing (APE) engine reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEGRA186_MEMORY_CLIENT_APER 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Audio Processing (APE) engine writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TEGRA186_MEMORY_CLIENT_APEW 0x7b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* SE Memory Return Data Client Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA186_MEMORY_CLIENT_SESRD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* SE Memory Write Client Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TEGRA186_MEMORY_CLIENT_SESWR 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* ETR reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA186_MEMORY_CLIENT_ETRR 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* ETR writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEGRA186_MEMORY_CLIENT_ETRW 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* TSECB Memory Return Data Client Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* TSECB Memory Write Client Description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* 3D, ltcx reads instance 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* 3D, ltcx writes instance 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* AXI Switch read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA186_MEMORY_CLIENT_AXISR 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* AXI Switch write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TEGRA186_MEMORY_CLIENT_AXISW 0x8d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* EQOS read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* EQOS write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* UFSHC read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* UFSHC write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* NVDISPLAY read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* BPMP read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TEGRA186_MEMORY_CLIENT_BPMPR 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* BPMP write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TEGRA186_MEMORY_CLIENT_BPMPW 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* BPMPDMA read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* BPMPDMA write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* AON read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TEGRA186_MEMORY_CLIENT_AONR 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* AON write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TEGRA186_MEMORY_CLIENT_AONW 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* AONDMA read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* AONDMA write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* SCE read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TEGRA186_MEMORY_CLIENT_SCER 0x9b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* SCE write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TEGRA186_MEMORY_CLIENT_SCEW 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* SCEDMA read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* SCEDMA write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* APEDMA read client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* APEDMA write client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* NVDISPLAY read client instance 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif