Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define DT_BINDINGS_MEMORY_TEGRA124_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define TEGRA_SWGROUP_PTC	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define TEGRA_SWGROUP_DC	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define TEGRA_SWGROUP_DCB	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define TEGRA_SWGROUP_AFI	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define TEGRA_SWGROUP_AVPC	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TEGRA_SWGROUP_HDA	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TEGRA_SWGROUP_HC	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TEGRA_SWGROUP_MSENC	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA_SWGROUP_PPCS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA_SWGROUP_SATA	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA_SWGROUP_VDE	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA_SWGROUP_MPCORELP	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA_SWGROUP_MPCORE	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA_SWGROUP_ISP2	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA_SWGROUP_XUSB_HOST	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA_SWGROUP_XUSB_DEV	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA_SWGROUP_ISP2B	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA_SWGROUP_TSEC	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA_SWGROUP_A9AVP	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA_SWGROUP_GPU	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA_SWGROUP_SDMMC1A	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA_SWGROUP_SDMMC2A	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA_SWGROUP_SDMMC3A	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA_SWGROUP_SDMMC4A	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_SWGROUP_VIC	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA_SWGROUP_VI	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA124_MC_RESET_AFI		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA124_MC_RESET_AVPC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA124_MC_RESET_DC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA124_MC_RESET_DCB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA124_MC_RESET_HC		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA124_MC_RESET_HDA		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA124_MC_RESET_ISP2		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA124_MC_RESET_MPCORE	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA124_MC_RESET_MPCORELP	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA124_MC_RESET_MSENC		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA124_MC_RESET_PPCS		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA124_MC_RESET_SATA		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA124_MC_RESET_VDE		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA124_MC_RESET_VI		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA124_MC_RESET_VIC		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA124_MC_RESET_XUSB_HOST	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA124_MC_RESET_XUSB_DEV	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA124_MC_RESET_TSEC		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA124_MC_RESET_SDMMC1	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA124_MC_RESET_SDMMC2	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA124_MC_RESET_SDMMC3	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA124_MC_RESET_SDMMC4	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA124_MC_RESET_ISP2B		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA124_MC_RESET_GPU		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif