^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/memory/rockchip-dram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PHY_DDR3_RON_DISABLE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PHY_DDR3_RON_455ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PHY_DDR3_RON_230ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PHY_DDR3_RON_153ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PHY_DDR3_RON_115ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PHY_DDR3_RON_91ohm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PHY_DDR3_RON_76ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PHY_DDR3_RON_65ohm (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PHY_DDR3_RON_57ohm (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PHY_DDR3_RON_51ohm (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PHY_DDR3_RON_46ohm (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PHY_DDR3_RON_41ohm (0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PHY_DDR3_RON_38ohm (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PHY_DDR3_RON_35ohm (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PHY_DDR3_RON_32ohm (0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PHY_DDR3_RON_30ohm (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PHY_DDR3_RON_28ohm (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PHY_DDR3_RON_27ohm (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PHY_DDR3_RON_25ohm (0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PHY_DDR3_RON_24ohm (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PHY_DDR3_RON_23ohm (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PHY_DDR3_RON_22ohm (0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHY_DDR3_RON_21ohm (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PHY_DDR3_RON_20ohm (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PHY_DDR3_RTT_DISABLE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PHY_DDR3_RTT_561ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PHY_DDR3_RTT_282ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PHY_DDR3_RTT_188ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PHY_DDR3_RTT_141ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PHY_DDR3_RTT_113ohm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PHY_DDR3_RTT_94ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PHY_DDR3_RTT_81ohm (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PHY_DDR3_RTT_72ohm (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PHY_DDR3_RTT_64ohm (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PHY_DDR3_RTT_58ohm (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PHY_DDR3_RTT_52ohm (0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PHY_DDR3_RTT_48ohm (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PHY_DDR3_RTT_44ohm (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PHY_DDR3_RTT_41ohm (0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PHY_DDR3_RTT_38ohm (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PHY_DDR3_RTT_37ohm (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PHY_DDR3_RTT_34ohm (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PHY_DDR3_RTT_32ohm (0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PHY_DDR3_RTT_31ohm (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PHY_DDR3_RTT_29ohm (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PHY_DDR3_RTT_28ohm (0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PHY_DDR3_RTT_27ohm (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PHY_DDR3_RTT_25ohm (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PHY_DDR4_LPDDR3_RON_DISABLE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PHY_DDR4_LPDDR3_RON_482ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PHY_DDR4_LPDDR3_RON_244ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PHY_DDR4_LPDDR3_RON_162ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PHY_DDR4_LPDDR3_RON_122ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PHY_DDR4_LPDDR3_RON_97ohm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PHY_DDR4_LPDDR3_RON_81ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PHY_DDR4_LPDDR3_RON_69ohm (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PHY_DDR4_LPDDR3_RON_61ohm (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PHY_DDR4_LPDDR3_RON_54ohm (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PHY_DDR4_LPDDR3_RON_48ohm (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PHY_DDR4_LPDDR3_RON_44ohm (0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PHY_DDR4_LPDDR3_RON_40ohm (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PHY_DDR4_LPDDR3_RON_37ohm (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PHY_DDR4_LPDDR3_RON_34ohm (0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PHY_DDR4_LPDDR3_RON_32ohm (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PHY_DDR4_LPDDR3_RON_30ohm (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PHY_DDR4_LPDDR3_RON_28ohm (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PHY_DDR4_LPDDR3_RON_27ohm (0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PHY_DDR4_LPDDR3_RON_25ohm (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PHY_DDR4_LPDDR3_RON_24ohm (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PHY_DDR4_LPDDR3_RON_23ohm (0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PHY_DDR4_LPDDR3_RON_22ohm (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PHY_DDR4_LPDDR3_RON_21ohm (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PHY_DDR4_LPDDR3_RTT_DISABLE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PHY_DDR4_LPDDR3_RTT_586ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PHY_DDR4_LPDDR3_RTT_294ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PHY_DDR4_LPDDR3_RTT_196ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PHY_DDR4_LPDDR3_RTT_148ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PHY_DDR4_LPDDR3_RTT_118ohm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PHY_DDR4_LPDDR3_RTT_99ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PHY_DDR4_LPDDR3_RTT_85ohm (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PHY_DDR4_LPDDR3_RTT_76ohm (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PHY_DDR4_LPDDR3_RTT_67ohm (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PHY_DDR4_LPDDR3_RTT_60ohm (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PHY_DDR4_LPDDR3_RTT_55ohm (0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PHY_DDR4_LPDDR3_RTT_50ohm (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PHY_DDR4_LPDDR3_RTT_46ohm (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PHY_DDR4_LPDDR3_RTT_43ohm (0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PHY_DDR4_LPDDR3_RTT_40ohm (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PHY_DDR4_LPDDR3_RTT_38ohm (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PHY_DDR4_LPDDR3_RTT_36ohm (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PHY_DDR4_LPDDR3_RTT_34ohm (0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PHY_DDR4_LPDDR3_RTT_32ohm (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PHY_DDR4_LPDDR3_RTT_31ohm (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PHY_DDR4_LPDDR3_RTT_29ohm (0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PHY_DDR4_LPDDR3_RTT_28ohm (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PHY_DDR4_LPDDR3_RTT_27ohm (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PHY_LPDDR4_RON_DISABLE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PHY_LPDDR4_RON_501ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PHY_LPDDR4_RON_253ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PHY_LPDDR4_RON_168ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PHY_LPDDR4_RON_126ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PHY_LPDDR4_RON_101ohm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PHY_LPDDR4_RON_84ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PHY_LPDDR4_RON_72ohm (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PHY_LPDDR4_RON_63ohm (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PHY_LPDDR4_RON_56ohm (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PHY_LPDDR4_RON_50ohm (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PHY_LPDDR4_RON_46ohm (0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PHY_LPDDR4_RON_42ohm (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PHY_LPDDR4_RON_38ohm (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PHY_LPDDR4_RON_36ohm (0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PHY_LPDDR4_RON_33ohm (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PHY_LPDDR4_RON_31ohm (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PHY_LPDDR4_RON_29ohm (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PHY_LPDDR4_RON_28ohm (0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PHY_LPDDR4_RON_26ohm (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PHY_LPDDR4_RON_25ohm (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PHY_LPDDR4_RON_24ohm (0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PHY_LPDDR4_RON_23ohm (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PHY_LPDDR4_RON_22ohm (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PHY_LPDDR4_RTT_DISABLE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PHY_LPDDR4_RTT_604ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PHY_LPDDR4_RTT_303ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PHY_LPDDR4_RTT_202ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PHY_LPDDR4_RTT_152ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PHY_LPDDR4_RTT_122ohm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PHY_LPDDR4_RTT_101ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PHY_LPDDR4_RTT_87ohm (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PHY_LPDDR4_RTT_78ohm (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PHY_LPDDR4_RTT_69ohm (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PHY_LPDDR4_RTT_62ohm (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PHY_LPDDR4_RTT_56ohm (0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PHY_LPDDR4_RTT_52ohm (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PHY_LPDDR4_RTT_48ohm (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PHY_LPDDR4_RTT_44ohm (0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PHY_LPDDR4_RTT_41ohm (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PHY_LPDDR4_RTT_39ohm (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PHY_LPDDR4_RTT_37ohm (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PHY_LPDDR4_RTT_35ohm (0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PHY_LPDDR4_RTT_33ohm (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PHY_LPDDR4_RTT_32ohm (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PHY_LPDDR4_RTT_30ohm (0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PHY_LPDDR4_RTT_29ohm (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PHY_LPDDR4_RTT_27ohm (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RV1126_H*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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