^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_DRAM_ROCKCHIP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DDR2_DS_FULL (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DDR2_DS_REDUCE (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DDR2_DS_MASK (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DDR2_ODT_DIS (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DDR2_ODT_75ohm (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DDR2_ODT_150ohm (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DDR2_ODT_50ohm ((0x1 << 6) | (0x1 << 2)) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DDR2_ODT_MASK ((0x1 << 2) | (0x1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DDR3_DS_40ohm (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DDR3_DS_34ohm (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DDR3_DS_MASK ((1 << 1) | (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DDR3_ODT_DIS (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DDR3_ODT_60ohm (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DDR3_ODT_120ohm (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DDR3_ODT_40ohm ((0x1 << 6) | (0x1 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DDR3_ODT_MASK ((0x1 << 2) | (0x1 << 6) | (0x1 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DDR4_DS_34ohm (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DDR4_DS_48ohm (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DDR4_DS_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DDR4_ODT_DIS (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DDR4_ODT_60ohm (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DDR4_ODT_120ohm (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DDR4_ODT_40ohm (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DDR4_ODT_240ohm (0x4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DDR4_ODT_48ohm (0x5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DDR4_ODT_80ohm (0x6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DDR4_ODT_34ohm (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DDR4_ODT_MASK (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LP2_DS_34ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LP2_DS_40ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LP2_DS_48ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LP2_DS_60ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LP2_DS_68_6ohm (0x5) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LP2_DS_80ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LP2_DS_120ohm (0x7) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LP2_DS_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LP3_DS_34ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LP3_DS_40ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LP3_DS_48ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LP3_DS_60ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LP3_DS_80ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LP3_DS_34D_40U (0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LP3_DS_40D_48U (0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LP3_DS_34D_48U (0xb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LP3_DS_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LP3_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LP3_ODT_60ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LP3_ODT_120ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LP3_ODT_240ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LP3_ODT_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LP4_PDDS_240ohm (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LP4_PDDS_120ohm (0x2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LP4_PDDS_80ohm (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LP4_PDDS_60ohm (0x4 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LP4_PDDS_48ohm (0x5 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LP4_PDDS_40ohm (0x6 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LP4_PDDS_MASK (0x7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LP4_DQ_ODT_DIS (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LP4_DQ_ODT_240ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LP4_DQ_ODT_120ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LP4_DQ_ODT_80ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LP4_DQ_ODT_60ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LP4_DQ_ODT_48ohm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LP4_DQ_ODT_40ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LP4_DQ_ODT_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LP4_CA_ODT_DIS (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LP4_CA_ODT_240ohm (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LP4_CA_ODT_120ohm (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LP4_CA_ODT_80ohm (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LP4_CA_ODT_60ohm (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LP4_CA_ODT_48ohm (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LP4_CA_ODT_40ohm (0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LP4_CA_ODT_MASK (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LP4_VDDQ_2_5 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LP4_VDDQ_3 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LP4X_VDDQ_0_6 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LP4X_VDDQ_0_5 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IGNORE_THIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif /* _DT_BINDINGS_DRAM_ROCKCHIP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags