^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3568_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_DRAM_ROCKCHIP_RK3568_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/memory/rockchip-dram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PHY_DDR4_DS_ODT_DISABLE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PHY_DDR4_DS_ODT_556ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PHY_DDR4_DS_ODT_279ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PHY_DDR4_DS_ODT_185ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PHY_DDR4_DS_ODT_139ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PHY_DDR4_DS_ODT_111ohm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PHY_DDR4_DS_ODT_93ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PHY_DDR4_DS_ODT_79ohm (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PHY_DDR4_DS_ODT_69ohm (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PHY_DDR4_DS_ODT_62ohm (0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PHY_DDR4_DS_ODT_55ohm (0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PHY_DDR4_DS_ODT_50ohm (0xb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PHY_DDR4_DS_ODT_46ohm (0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PHY_DDR4_DS_ODT_42ohm (0xd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PHY_DDR4_DS_ODT_39ohm (0xe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PHY_DDR4_DS_ODT_37ohm (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PHY_DDR4_DS_ODT_34ohm (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PHY_DDR4_DS_ODT_32ohm (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PHY_DDR4_DS_ODT_31ohm (0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PHY_DDR4_DS_ODT_29ohm (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PHY_DDR4_DS_ODT_27ohm (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PHY_DDR4_DS_ODT_26ohm (0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHY_DDR4_DS_ODT_25ohm (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PHY_DDR4_DS_ODT_24ohm (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PHY_LPDDR4_DS_ODT_DISABLE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PHY_LPDDR4_DS_ODT_576ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PHY_LPDDR4_DS_ODT_289ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PHY_LPDDR4_DS_ODT_192ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PHY_LPDDR4_DS_ODT_144ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PHY_LPDDR4_DS_ODT_115ohm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PHY_LPDDR4_DS_ODT_96ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PHY_LPDDR4_DS_ODT_82ohm (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PHY_LPDDR4_DS_ODT_72ohm (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PHY_LPDDR4_DS_ODT_64ohm (0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PHY_LPDDR4_DS_ODT_57ohm (0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PHY_LPDDR4_DS_ODT_52ohm (0xb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PHY_LPDDR4_DS_ODT_48ohm (0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PHY_LPDDR4_DS_ODT_44ohm (0xd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PHY_LPDDR4_DS_ODT_41ohm (0xe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PHY_LPDDR4_DS_ODT_38ohm (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PHY_LPDDR4_DS_ODT_36ohm (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PHY_LPDDR4_DS_ODT_34ohm (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PHY_LPDDR4_DS_ODT_32ohm (0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PHY_LPDDR4_DS_ODT_30ohm (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PHY_LPDDR4_DS_ODT_28ohm (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PHY_LPDDR4_DS_ODT_27ohm (0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PHY_LPDDR4_DS_ODT_26ohm (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PHY_LPDDR4_DS_ODT_25ohm (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PHY_LPDDR4X_DS_ODT_UP_DISABLE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PHY_LPDDR4X_DS_ODT_UP_646ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PHY_LPDDR4X_DS_ODT_UP_323ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PHY_LPDDR4X_DS_ODT_UP_215ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PHY_LPDDR4X_DS_ODT_UP_162ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PHY_LPDDR4X_DS_ODT_UP_129ohm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PHY_LPDDR4X_DS_ODT_UP_108ohm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PHY_LPDDR4X_DS_ODT_UP_92ohm (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PHY_LPDDR4X_DS_ODT_UP_81ohm (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PHY_LPDDR4X_DS_ODT_UP_72ohm (0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PHY_LPDDR4X_DS_ODT_UP_65ohm (0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PHY_LPDDR4X_DS_ODT_UP_59ohm (0xb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PHY_LPDDR4X_DS_ODT_UP_54ohm (0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PHY_LPDDR4X_DS_ODT_UP_50ohm (0xd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PHY_LPDDR4X_DS_ODT_UP_46ohm (0xe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PHY_LPDDR4X_DS_ODT_UP_43ohm (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PHY_LPDDR4X_DS_ODT_UP_40ohm (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PHY_LPDDR4X_DS_ODT_UP_38ohm (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PHY_LPDDR4X_DS_ODT_UP_36ohm (0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PHY_LPDDR4X_DS_ODT_UP_34ohm (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PHY_LPDDR4X_DS_ODT_UP_32ohm (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PHY_LPDDR4X_DS_ODT_UP_31ohm (0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PHY_LPDDR4X_DS_ODT_UP_29ohm (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PHY_LPDDR4X_DS_ODT_UP_28ohm (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PHY_LPDDR4X_DS_ODT_DOWN_DISABLE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PHY_LPDDR4X_DS_ODT_DOWN_513ohm (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PHY_LPDDR4X_DS_ODT_DOWN_259ohm (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PHY_LPDDR4X_DS_ODT_DOWN_172ohm (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PHY_LPDDR4X_DS_ODT_DOWN_130ohm (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PHY_LPDDR4X_DS_ODT_DOWN_104hm (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PHY_LPDDR4X_DS_ODT_DOWN_86hm (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PHY_LPDDR4X_DS_ODT_DOWN_74ohm (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PHY_LPDDR4X_DS_ODT_DOWN_65ohm (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PHY_LPDDR4X_DS_ODT_DOWN_58ohm (0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PHY_LPDDR4X_DS_ODT_DOWN_52ohm (0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PHY_LPDDR4X_DS_ODT_DOWN_47ohm (0xb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PHY_LPDDR4X_DS_ODT_DOWN_43ohm (0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PHY_LPDDR4X_DS_ODT_DOWN_40ohm (0xd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PHY_LPDDR4X_DS_ODT_DOWN_37ohm (0xe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PHY_LPDDR4X_DS_ODT_DOWN_35ohm (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PHY_LPDDR4X_DS_ODT_DOWN_32ohm (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PHY_LPDDR4X_DS_ODT_DOWN_30ohm (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PHY_LPDDR4X_DS_ODT_DOWN_29ohm (0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PHY_LPDDR4X_DS_ODT_DOWN_27ohm (0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PHY_LPDDR4X_DS_ODT_DOWN_26ohm (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PHY_LPDDR4X_DS_ODT_DOWN_25ohm (0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PHY_LPDDR4X_DS_ODT_DOWN_24ohm (0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PHY_LPDDR4X_DS_ODT_DOWN_23ohm (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK3568_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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