Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This file is dual-licensed: you can use it either under the terms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * of the GPL or the X11 license, at your option. Note that this dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * licensing only applies to this file, and not this project as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * whole.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  a) This library is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *     modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *     published by the Free Software Foundation; either version 2 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *     License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *     This library is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *     GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Or, alternatively,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *  b) Permission is hereby granted, free of charge, to any person
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *     obtaining a copy of this software and associated documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *     files (the "Software"), to deal in the Software without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *     restriction, including without limitation the rights to use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *     copy, modify, merge, publish, distribute, sublicense, and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *     sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *     Software is furnished to do so, subject to the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *     conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *     The above copyright notice and this permission notice shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *     included in all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *     OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3399_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define _DT_BINDINGS_DRAM_ROCKCHIP_RK3399_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DDR3_DS_34ohm		(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DDR3_DS_40ohm		(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DDR3_ODT_DIS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DDR3_ODT_40ohm		(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DDR3_ODT_60ohm		(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DDR3_ODT_120ohm		(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define LP2_DS_34ohm		(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define LP2_DS_40ohm		(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define LP2_DS_48ohm		(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define LP2_DS_60ohm		(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define LP2_DS_68_6ohm		(68)	/* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define LP2_DS_80ohm		(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define LP2_DS_120ohm		(120)	/* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define LP3_DS_34ohm		(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define LP3_DS_40ohm		(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define LP3_DS_48ohm		(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define LP3_DS_60ohm		(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define LP3_DS_80ohm		(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define LP3_DS_34D_40U		(3440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define LP3_DS_40D_48U		(4048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define LP3_DS_34D_48U		(3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define LP3_ODT_DIS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define LP3_ODT_60ohm		(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define LP3_ODT_120ohm		(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define LP3_ODT_240ohm		(240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define LP4_PDDS_40ohm		(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define LP4_PDDS_48ohm		(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define LP4_PDDS_60ohm		(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define LP4_PDDS_80ohm		(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define LP4_PDDS_120ohm		(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define LP4_PDDS_240ohm		(240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define LP4_DQ_ODT_40ohm	(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define LP4_DQ_ODT_48ohm	(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define LP4_DQ_ODT_60ohm	(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define LP4_DQ_ODT_80ohm	(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define LP4_DQ_ODT_120ohm	(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define LP4_DQ_ODT_240ohm	(240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define LP4_DQ_ODT_DIS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define LP4_CA_ODT_40ohm	(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define LP4_CA_ODT_48ohm	(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define LP4_CA_ODT_60ohm	(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define LP4_CA_ODT_80ohm	(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define LP4_CA_ODT_120ohm	(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define LP4_CA_ODT_240ohm	(240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define LP4_CA_ODT_DIS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define PHY_DRV_ODT_Hi_Z	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PHY_DRV_ODT_240		(240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PHY_DRV_ODT_120		(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PHY_DRV_ODT_80		(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PHY_DRV_ODT_60		(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PHY_DRV_ODT_48		(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PHY_DRV_ODT_40		(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PHY_DRV_ODT_34_3	(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK3399_H */