^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is dual-licensed: you can use it either under the terms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * of the GPL or the X11 license, at your option. Note that this dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * licensing only applies to this file, and not this project as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * whole.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * a) This library is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation; either version 2 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This library is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Or, alternatively,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * b) Permission is hereby granted, free of charge, to any person
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * obtaining a copy of this software and associated documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * files (the "Software"), to deal in the Software without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * restriction, including without limitation the rights to use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * copy, modify, merge, publish, distribute, sublicense, and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Software is furnished to do so, subject to the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * The above copyright notice and this permission notice shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * included in all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DDR3_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DDR3_DS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DDR3_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DDR3_ODT_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DDR3_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DDR3_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LP2_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LP2_DS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LP2_DS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LP2_DS_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LP2_DS_68_6ohm (68) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LP2_DS_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LP2_DS_120ohm (120) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LP3_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LP3_DS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LP3_DS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LP3_DS_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LP3_DS_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LP3_DS_34D_40U (3440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LP3_DS_40D_48U (4048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LP3_DS_34D_48U (3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LP3_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LP3_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LP3_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LP3_ODT_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LP4_PDDS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LP4_PDDS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LP4_PDDS_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LP4_PDDS_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LP4_PDDS_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LP4_PDDS_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LP4_DQ_ODT_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LP4_DQ_ODT_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LP4_DQ_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LP4_DQ_ODT_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LP4_DQ_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LP4_DQ_ODT_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LP4_DQ_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LP4_CA_ODT_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LP4_CA_ODT_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LP4_CA_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define LP4_CA_ODT_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LP4_CA_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LP4_CA_ODT_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LP4_CA_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DDR4_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DDR4_DS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DDR4_RTT_NOM_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DDR4_RTT_NOM_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DDR4_RTT_NOM_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DDR4_RTT_NOM_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DDR4_RTT_NOM_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DDR4_RTT_NOM_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DDR4_RTT_NOM_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DDR4_RTT_NOM_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PHY_DDR3_RON_RTT_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PHY_DDR3_RON_RTT_451ohm (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PHY_DDR3_RON_RTT_225ohm (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PHY_DDR3_RON_RTT_150ohm (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PHY_DDR3_RON_RTT_112ohm (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PHY_DDR3_RON_RTT_90ohm (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PHY_DDR3_RON_RTT_75ohm (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PHY_DDR3_RON_RTT_64ohm (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PHY_DDR3_RON_RTT_56ohm (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PHY_DDR3_RON_RTT_50ohm (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PHY_DDR3_RON_RTT_45ohm (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PHY_DDR3_RON_RTT_41ohm (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PHY_DDR3_RON_RTT_37ohm (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PHY_DDR3_RON_RTT_34ohm (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PHY_DDR3_RON_RTT_33ohm (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PHY_DDR3_RON_RTT_30ohm (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PHY_DDR3_RON_RTT_28ohm (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PHY_DDR3_RON_RTT_26ohm (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PHY_DDR3_RON_RTT_25ohm (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PHY_DDR3_RON_RTT_23ohm (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PHY_DDR3_RON_RTT_22ohm (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PHY_DDR3_RON_RTT_21ohm (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PHY_DDR3_RON_RTT_20ohm (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PHY_DDR3_RON_RTT_19ohm (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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