^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DDR2_DS_FULL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DDR2_DS_REDUCE (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DDR2_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DDR2_ODT_50ohm (50) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DDR2_ODT_75ohm (75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DDR2_ODT_150ohm (150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DDR3_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DDR3_DS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DDR3_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DDR3_ODT_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DDR3_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DDR3_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LP2_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LP2_DS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LP2_DS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LP2_DS_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LP2_DS_68_6ohm (68) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LP2_DS_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LP2_DS_120ohm (120) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LP3_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LP3_DS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LP3_DS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LP3_DS_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LP3_DS_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LP3_DS_34D_40U (3440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LP3_DS_40D_48U (4048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LP3_DS_34D_48U (3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LP3_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LP3_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LP3_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LP3_ODT_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LP4_PDDS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LP4_PDDS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LP4_PDDS_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LP4_PDDS_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LP4_PDDS_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LP4_PDDS_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LP4_DQ_ODT_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LP4_DQ_ODT_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LP4_DQ_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LP4_DQ_ODT_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LP4_DQ_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LP4_DQ_ODT_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LP4_DQ_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LP4_CA_ODT_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LP4_CA_ODT_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LP4_CA_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LP4_CA_ODT_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LP4_CA_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LP4_CA_ODT_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LP4_CA_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DDR4_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DDR4_DS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DDR4_RTT_NOM_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DDR4_RTT_NOM_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DDR4_RTT_NOM_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DDR4_RTT_NOM_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DDR4_RTT_NOM_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DDR4_RTT_NOM_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DDR4_RTT_NOM_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DDR4_RTT_NOM_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PHY_DDR3_RON_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PHY_DDR3_RON_340ohm (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PHY_DDR3_RON_170ohm (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PHY_DDR3_RON_113ohm (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PHY_DDR3_RON_85ohm (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PHY_DDR3_RON_68ohm (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PHY_DDR3_RON_57ohm (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PHY_DDR3_RON_49ohm (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PHY_DDR3_RON_43ohm (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PHY_DDR3_RON_38ohm (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PHY_DDR3_RON_34ohm (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PHY_DDR3_RON_31ohm (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PHY_DDR3_RON_28ohm (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PHY_DDR3_RON_26ohm (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PHY_DDR3_RON_24ohm (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PHY_DDR3_RON_23ohm (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PHY_DDR3_RON_21ohm (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PHY_DDR3_RON_20ohm (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PHY_DDR3_RON_19ohm (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PHY_DDR3_RON_18ohm (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PHY_DDR3_RON_17ohm (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PHY_DDR3_RON_16ohm (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PHY_DDR3_RON_15ohm (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PHY_DDR3_RTT_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PHY_DDR3_RTT_852ohm (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PHY_DDR3_RTT_427ohm (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PHY_DDR3_RTT_284ohm (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PHY_DDR3_RTT_213ohm (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PHY_DDR3_RTT_171ohm (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PHY_DDR3_RTT_142ohm (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PHY_DDR3_RTT_122ohm (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PHY_DDR3_RTT_107ohm (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PHY_DDR3_RTT_95ohm (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PHY_DDR3_RTT_85ohm (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PHY_DDR3_RTT_78ohm (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PHY_DDR3_RTT_71ohm (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PHY_DDR3_RTT_66ohm (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PHY_DDR3_RTT_61ohm (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PHY_DDR3_RTT_57ohm (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PHY_DDR3_RTT_53ohm (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PHY_DDR3_RTT_50ohm (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PHY_DDR3_RTT_47ohm (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PHY_DDR3_RTT_45ohm (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PHY_DDR3_RTT_43ohm (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PHY_DDR3_RTT_41ohm (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PHY_DDR3_RTT_39ohm (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PHY_DDR3_RTT_37ohm (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PHY_DDR4_LPDDR2_3_RON_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PHY_DDR4_LPDDR2_3_RON_376ohm (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PHY_DDR4_LPDDR2_3_RON_188ohm (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PHY_DDR4_LPDDR2_3_RON_125ohm (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PHY_DDR4_LPDDR2_3_RON_94ohm (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PHY_DDR4_LPDDR2_3_RON_75ohm (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PHY_DDR4_LPDDR2_3_RON_63ohm (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PHY_DDR4_LPDDR2_3_RON_54ohm (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PHY_DDR4_LPDDR2_3_RON_47ohm (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PHY_DDR4_LPDDR2_3_RON_42ohm (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PHY_DDR4_LPDDR2_3_RON_38ohm (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PHY_DDR4_LPDDR2_3_RON_34ohm (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PHY_DDR4_LPDDR2_3_RON_31ohm (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PHY_DDR4_LPDDR2_3_RON_29ohm (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PHY_DDR4_LPDDR2_3_RON_27ohm (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PHY_DDR4_LPDDR2_3_RON_25ohm (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PHY_DDR4_LPDDR2_3_RON_23ohm (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PHY_DDR4_LPDDR2_3_RON_22ohm (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PHY_DDR4_LPDDR2_3_RON_21ohm (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PHY_DDR4_LPDDR2_3_RON_20ohm (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PHY_DDR4_LPDDR2_3_RON_19ohm (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PHY_DDR4_LPDDR2_3_RON_18ohm (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PHY_DDR4_LPDDR2_3_RON_17ohm (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PHY_DDR4_LPDDR2_3_RON_16ohm (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PHY_DDR4_LPDDR2_3_RTT_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PHY_DDR4_LPDDR2_3_RTT_915ohm (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PHY_DDR4_LPDDR2_3_RTT_458ohm (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PHY_DDR4_LPDDR2_3_RTT_305ohm (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PHY_DDR4_LPDDR2_3_RTT_229ohm (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PHY_DDR4_LPDDR2_3_RTT_183ohm (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PHY_DDR4_LPDDR2_3_RTT_153ohm (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PHY_DDR4_LPDDR2_3_RTT_131ohm (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PHY_DDR4_LPDDR2_3_RTT_115ohm (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PHY_DDR4_LPDDR2_3_RTT_102ohm (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PHY_DDR4_LPDDR2_3_RTT_92ohm (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PHY_DDR4_LPDDR2_3_RTT_83ohm (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PHY_DDR4_LPDDR2_3_RTT_76ohm (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PHY_DDR4_LPDDR2_3_RTT_70ohm (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PHY_DDR4_LPDDR2_3_RTT_65ohm (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PHY_DDR4_LPDDR2_3_RTT_61ohm (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PHY_DDR4_LPDDR2_3_RTT_57ohm (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PHY_DDR4_LPDDR2_3_RTT_54ohm (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PHY_DDR4_LPDDR2_3_RTT_51ohm (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PHY_DDR4_LPDDR2_3_RTT_48ohm (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PHY_DDR4_LPDDR2_3_RTT_46ohm (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PHY_DDR4_LPDDR2_3_RTT_44ohm (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PHY_DDR4_LPDDR2_3_RTT_42ohm (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PHY_DDR4_LPDDR2_3_RTT_40ohm (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK1808_H*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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