^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_PX30_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_DRAM_ROCKCHIP_PX30_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DDR2_DS_FULL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DDR2_DS_REDUCE (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DDR2_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DDR2_ODT_50ohm (50) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DDR2_ODT_75ohm (75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DDR2_ODT_150ohm (150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DDR3_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DDR3_DS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DDR3_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DDR3_ODT_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DDR3_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DDR3_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LP2_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LP2_DS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LP2_DS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LP2_DS_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LP2_DS_68_6ohm (68) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LP2_DS_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LP2_DS_120ohm (120) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LP3_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LP3_DS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LP3_DS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LP3_DS_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LP3_DS_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LP3_DS_34D_40U (3440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LP3_DS_40D_48U (4048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LP3_DS_34D_48U (3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LP3_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LP3_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LP3_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LP3_ODT_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LP4_PDDS_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LP4_PDDS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LP4_PDDS_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LP4_PDDS_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LP4_PDDS_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LP4_PDDS_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LP4_DQ_ODT_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LP4_DQ_ODT_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LP4_DQ_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LP4_DQ_ODT_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LP4_DQ_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LP4_DQ_ODT_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LP4_DQ_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LP4_CA_ODT_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LP4_CA_ODT_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LP4_CA_ODT_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LP4_CA_ODT_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LP4_CA_ODT_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LP4_CA_ODT_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LP4_CA_ODT_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DDR4_DS_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DDR4_DS_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DDR4_RTT_NOM_DIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DDR4_RTT_NOM_60ohm (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DDR4_RTT_NOM_120ohm (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DDR4_RTT_NOM_40ohm (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DDR4_RTT_NOM_240ohm (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DDR4_RTT_NOM_48ohm (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DDR4_RTT_NOM_80ohm (80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DDR4_RTT_NOM_34ohm (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PHY_DDR3_RON_RTT_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PHY_DDR3_RON_RTT_451ohm (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PHY_DDR3_RON_RTT_225ohm (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PHY_DDR3_RON_RTT_150ohm (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PHY_DDR3_RON_RTT_112ohm (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PHY_DDR3_RON_RTT_90ohm (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PHY_DDR3_RON_RTT_75ohm (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PHY_DDR3_RON_RTT_64ohm (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PHY_DDR3_RON_RTT_56ohm (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PHY_DDR3_RON_RTT_50ohm (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PHY_DDR3_RON_RTT_45ohm (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PHY_DDR3_RON_RTT_41ohm (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PHY_DDR3_RON_RTT_37ohm (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PHY_DDR3_RON_RTT_34ohm (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PHY_DDR3_RON_RTT_33ohm (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PHY_DDR3_RON_RTT_30ohm (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PHY_DDR3_RON_RTT_28ohm (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PHY_DDR3_RON_RTT_26ohm (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PHY_DDR3_RON_RTT_25ohm (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PHY_DDR3_RON_RTT_23ohm (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PHY_DDR3_RON_RTT_22ohm (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PHY_DDR3_RON_RTT_21ohm (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PHY_DDR3_RON_RTT_20ohm (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PHY_DDR3_RON_RTT_19ohm (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PHY_DDR4_LPDDR3_2_RON_RTT_DISABLE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PHY_DDR4_LPDDR3_2_RON_RTT_480ohm (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PHY_DDR4_LPDDR3_2_RON_RTT_240ohm (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PHY_DDR4_LPDDR3_2_RON_RTT_160ohm (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PHY_DDR4_LPDDR3_2_RON_RTT_120ohm (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PHY_DDR4_LPDDR3_2_RON_RTT_96ohm (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PHY_DDR4_LPDDR3_2_RON_RTT_80ohm (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PHY_DDR4_LPDDR3_2_RON_RTT_68ohm (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PHY_DDR4_LPDDR3_2_RON_RTT_60ohm (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PHY_DDR4_LPDDR3_2_RON_RTT_53ohm (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PHY_DDR4_LPDDR3_2_RON_RTT_48ohm (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PHY_DDR4_LPDDR3_2_RON_RTT_43ohm (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PHY_DDR4_LPDDR3_2_RON_RTT_40ohm (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PHY_DDR4_LPDDR3_2_RON_RTT_37ohm (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PHY_DDR4_LPDDR3_2_RON_RTT_34ohm (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PHY_DDR4_LPDDR3_2_RON_RTT_32ohm (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PHY_DDR4_LPDDR3_2_RON_RTT_30ohm (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PHY_DDR4_LPDDR3_2_RON_RTT_28ohm (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PHY_DDR4_LPDDR3_2_RON_RTT_26ohm (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PHY_DDR4_LPDDR3_2_RON_RTT_25ohm (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PHY_DDR4_LPDDR3_2_RON_RTT_24ohm (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PHY_DDR4_LPDDR3_2_RON_RTT_22ohm (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PHY_DDR4_LPDDR3_2_RON_RTT_21ohm (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PHY_DDR4_LPDDR3_2_RON_RTT_20ohm (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LP4_VDDQ_2_5 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LP4_VDDQ_3 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LP4X_VDDQ_0_6 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LP4X_VDDQ_0_5 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IGNORE_THIS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_PX30_H*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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