Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides constants for binding nvidia,tegra186-hsp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * These define the type of mailbox that is to be used (doorbell, shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * mailbox, shared semaphore or arbitrated semaphore).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA_HSP_MBOX_TYPE_DB 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA_HSP_MBOX_TYPE_SM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA_HSP_MBOX_TYPE_SS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA_HSP_MBOX_TYPE_AS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * These defines represent the bit associated with the given master ID in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * doorbell registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA_HSP_DB_MASTER_CCPLEX 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA_HSP_DB_MASTER_BPMP 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * Shared mailboxes are unidirectional, so the direction needs to be specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * in the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_HSP_SM_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA_HSP_SM_FLAG_RX (0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA_HSP_SM_FLAG_TX (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA_HSP_SM_RX(x) (TEGRA_HSP_SM_FLAG_RX | ((x) & TEGRA_HSP_SM_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA_HSP_SM_TX(x) (TEGRA_HSP_SM_FLAG_TX | ((x) & TEGRA_HSP_SM_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif