^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define ASPEED_SCU_IC_VGA_CURSOR_CHANGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define ASPEED_SCU_IC_VGA_SCRATCH_REG_CHANGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ASPEED_AST2500_SCU_IC_PCIE_RESET_HI_TO_LO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ASPEED_AST2500_SCU_IC_LPC_RESET_LO_TO_HI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ASPEED_AST2500_SCU_IC_LPC_RESET_HI_TO_LO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ASPEED_AST2500_SCU_IC_ISSUE_MSI 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ASPEED_AST2600_SCU_IC0_PCIE_PERST_HI_TO_LO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_LO_TO_HI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_HI_TO_LO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */