^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm SM8150 interconnect IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MASTER_A1NOC_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MASTER_QUP_0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MASTER_EMAC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MASTER_UFS_MEM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MASTER_USB3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MASTER_USB3_1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define A1NOC_SNOC_SLV 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SLAVE_SERVICE_A1NOC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MASTER_A2NOC_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MASTER_QDSS_BAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MASTER_QSPI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MASTER_QUP_1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MASTER_QUP_2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MASTER_SENSORS_AHB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MASTER_TSIF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MASTER_CNOC_A2NOC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MASTER_CRYPTO_CORE_0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MASTER_IPA 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MASTER_PCIE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MASTER_PCIE_1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MASTER_QDSS_ETR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MASTER_SDCC_2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MASTER_SDCC_4 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define A2NOC_SNOC_SLV 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SLAVE_ANOC_PCIE_GEM_NOC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SLAVE_SERVICE_A2NOC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MASTER_CAMNOC_HF0_UNCOMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MASTER_CAMNOC_HF1_UNCOMP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MASTER_CAMNOC_SF_UNCOMP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SLAVE_CAMNOC_UNCOMP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MASTER_NPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SLAVE_CDSP_MEM_NOC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MASTER_SPDM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SNOC_CNOC_MAS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MASTER_QDSS_DAP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SLAVE_A1NOC_CFG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SLAVE_A2NOC_CFG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SLAVE_AHB2PHY_SOUTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SLAVE_AOP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SLAVE_AOSS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SLAVE_CAMERA_CFG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SLAVE_CLK_CTL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SLAVE_CDSP_CFG 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SLAVE_RBCPR_CX_CFG 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SLAVE_RBCPR_MMCX_CFG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SLAVE_RBCPR_MX_CFG 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SLAVE_CRYPTO_0_CFG 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SLAVE_CNOC_DDRSS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SLAVE_DISPLAY_CFG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SLAVE_EMAC_CFG 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SLAVE_GLM 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SLAVE_GRAPHICS_3D_CFG 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SLAVE_IMEM_CFG 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SLAVE_IPA_CFG 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SLAVE_CNOC_MNOC_CFG 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SLAVE_NPU_CFG 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SLAVE_PCIE_0_CFG 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SLAVE_PCIE_1_CFG 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SLAVE_NORTH_PHY_CFG 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SLAVE_PIMEM_CFG 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SLAVE_PRNG 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SLAVE_QDSS_CFG 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SLAVE_QSPI 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SLAVE_QUP_2 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SLAVE_QUP_1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SLAVE_QUP_0 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SLAVE_SDCC_2 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SLAVE_SDCC_4 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SLAVE_SNOC_CFG 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SLAVE_SPDM_WRAPPER 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SLAVE_SPSS_CFG 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SLAVE_SSC_CFG 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SLAVE_TCSR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SLAVE_TLMM_EAST 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SLAVE_TLMM_NORTH 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SLAVE_TLMM_SOUTH 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SLAVE_TLMM_WEST 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SLAVE_TSIF 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SLAVE_UFS_CARD_CFG 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SLAVE_UFS_MEM_CFG 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SLAVE_USB3 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SLAVE_USB3_1 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SLAVE_VENUS_CFG 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SLAVE_VSENSE_CTRL_CFG 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SLAVE_CNOC_A2NOC 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SLAVE_SERVICE_CNOC 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MASTER_CNOC_DC_NOC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SLAVE_LLCC_CFG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SLAVE_GEM_NOC_CFG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MASTER_AMPSS_M0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MASTER_GPU_TCU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MASTER_SYS_TCU 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MASTER_GEM_NOC_CFG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MASTER_COMPUTE_NOC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MASTER_GRAPHICS_3D 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MASTER_MNOC_HF_MEM_NOC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MASTER_MNOC_SF_MEM_NOC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MASTER_GEM_NOC_PCIE_SNOC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MASTER_SNOC_GC_MEM_NOC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MASTER_SNOC_SF_MEM_NOC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MASTER_ECC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SLAVE_MSS_PROC_MS_MPU_CFG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SLAVE_ECC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SLAVE_GEM_NOC_SNOC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SLAVE_LLCC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SLAVE_SERVICE_GEM_NOC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MASTER_IPA_CORE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SLAVE_IPA_CORE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MASTER_LLCC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SLAVE_EBI_CH0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MASTER_CNOC_MNOC_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MASTER_CAMNOC_HF0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MASTER_CAMNOC_HF1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MASTER_CAMNOC_SF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MASTER_MDP_PORT0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MASTER_MDP_PORT1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MASTER_ROTATOR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MASTER_VIDEO_P0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MASTER_VIDEO_P1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MASTER_VIDEO_PROC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SLAVE_MNOC_SF_MEM_NOC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SLAVE_MNOC_HF_MEM_NOC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SLAVE_SERVICE_MNOC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MASTER_SNOC_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define A1NOC_SNOC_MAS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define A2NOC_SNOC_MAS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MASTER_GEM_NOC_SNOC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MASTER_PIMEM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MASTER_GIC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SLAVE_APPSS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SNOC_CNOC_SLV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SLAVE_SNOC_GEM_NOC_GC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SLAVE_SNOC_GEM_NOC_SF 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SLAVE_OCIMEM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SLAVE_PIMEM 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SLAVE_SERVICE_SNOC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SLAVE_PCIE_0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SLAVE_PCIE_1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SLAVE_QDSS_STM 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SLAVE_TCU 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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