^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm SDM845 interconnect IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018, Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Georgi Djakov <georgi.djakov@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MASTER_A1NOC_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MASTER_TSIF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MASTER_SDCC_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MASTER_SDCC_4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MASTER_UFS_CARD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MASTER_UFS_MEM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MASTER_PCIE_0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SLAVE_A1NOC_SNOC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SLAVE_SERVICE_A1NOC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SLAVE_ANOC_PCIE_A1NOC_SNOC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MASTER_A2NOC_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MASTER_QDSS_BAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MASTER_CNOC_A2NOC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MASTER_CRYPTO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MASTER_IPA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MASTER_PCIE_1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MASTER_QDSS_ETR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MASTER_USB3_0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MASTER_USB3_1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SLAVE_A2NOC_SNOC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SLAVE_ANOC_PCIE_SNOC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SLAVE_SERVICE_A2NOC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MASTER_SPDM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MASTER_TIC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MASTER_SNOC_CNOC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MASTER_QDSS_DAP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SLAVE_A1NOC_CFG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SLAVE_A2NOC_CFG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SLAVE_AOP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SLAVE_AOSS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SLAVE_CAMERA_CFG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SLAVE_CLK_CTL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SLAVE_CDSP_CFG 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SLAVE_RBCPR_CX_CFG 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SLAVE_CRYPTO_0_CFG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SLAVE_DCC_CFG 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SLAVE_CNOC_DDRSS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SLAVE_DISPLAY_CFG 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SLAVE_GLM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SLAVE_GFX3D_CFG 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SLAVE_IMEM_CFG 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SLAVE_IPA_CFG 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SLAVE_CNOC_MNOC_CFG 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SLAVE_PCIE_0_CFG 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SLAVE_PCIE_1_CFG 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SLAVE_PDM 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SLAVE_SOUTH_PHY_CFG 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SLAVE_PIMEM_CFG 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SLAVE_PRNG 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SLAVE_QDSS_CFG 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SLAVE_BLSP_2 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SLAVE_BLSP_1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SLAVE_SDCC_2 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SLAVE_SDCC_4 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SLAVE_SNOC_CFG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SLAVE_SPDM_WRAPPER 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SLAVE_SPSS_CFG 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SLAVE_TCSR 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SLAVE_TLMM_NORTH 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SLAVE_TLMM_SOUTH 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SLAVE_TSIF 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SLAVE_UFS_CARD_CFG 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SLAVE_UFS_MEM_CFG 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SLAVE_USB3_0 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SLAVE_USB3_1 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SLAVE_VENUS_CFG 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SLAVE_VSENSE_CTRL_CFG 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SLAVE_CNOC_A2NOC 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SLAVE_SERVICE_CNOC 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MASTER_CNOC_DC_NOC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SLAVE_LLCC_CFG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SLAVE_MEM_NOC_CFG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MASTER_APPSS_PROC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MASTER_GNOC_CFG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SLAVE_GNOC_SNOC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SLAVE_GNOC_MEM_NOC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SLAVE_SERVICE_GNOC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MASTER_TCU_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MASTER_MEM_NOC_CFG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MASTER_GNOC_MEM_NOC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MASTER_MNOC_HF_MEM_NOC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MASTER_MNOC_SF_MEM_NOC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MASTER_SNOC_GC_MEM_NOC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MASTER_SNOC_SF_MEM_NOC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MASTER_GFX3D 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SLAVE_MSS_PROC_MS_MPU_CFG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SLAVE_MEM_NOC_GNOC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SLAVE_LLCC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SLAVE_MEM_NOC_SNOC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SLAVE_SERVICE_MEM_NOC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MASTER_LLCC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SLAVE_EBI1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MASTER_CNOC_MNOC_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MASTER_CAMNOC_HF0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MASTER_CAMNOC_HF1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MASTER_CAMNOC_SF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MASTER_MDP0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MASTER_MDP1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MASTER_ROTATOR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MASTER_VIDEO_P0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MASTER_VIDEO_P1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MASTER_VIDEO_PROC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SLAVE_MNOC_SF_MEM_NOC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SLAVE_MNOC_HF_MEM_NOC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SLAVE_SERVICE_MNOC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MASTER_CAMNOC_HF0_UNCOMP 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MASTER_CAMNOC_HF1_UNCOMP 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MASTER_CAMNOC_SF_UNCOMP 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SLAVE_CAMNOC_UNCOMP 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MASTER_SNOC_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MASTER_A1NOC_SNOC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MASTER_A2NOC_SNOC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MASTER_GNOC_SNOC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MASTER_MEM_NOC_SNOC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MASTER_ANOC_PCIE_SNOC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MASTER_PIMEM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MASTER_GIC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SLAVE_APPSS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SLAVE_SNOC_CNOC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SLAVE_SNOC_MEM_NOC_GC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SLAVE_SNOC_MEM_NOC_SF 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SLAVE_IMEM 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SLAVE_PCIE_0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SLAVE_PCIE_1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SLAVE_PIMEM 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SLAVE_SERVICE_SNOC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SLAVE_QDSS_STM 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SLAVE_TCU 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags