^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm msm8974 interconnect IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019 Brian Masney <masneyb@onstation.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BIMC_MAS_AMPSS_M0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BIMC_MAS_AMPSS_M1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BIMC_MAS_MSS_PROC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BIMC_TO_MNOC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BIMC_TO_SNOC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BIMC_SLV_EBI_CH0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BIMC_SLV_AMPSS_L2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CNOC_MAS_RPM_INST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CNOC_MAS_RPM_DATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CNOC_MAS_RPM_SYS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CNOC_MAS_DEHR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CNOC_MAS_QDSS_DAP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CNOC_MAS_SPDM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CNOC_MAS_TIC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CNOC_SLV_CLK_CTL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CNOC_SLV_CNOC_MSS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CNOC_SLV_SECURITY 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CNOC_SLV_TCSR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CNOC_SLV_TLMM 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CNOC_SLV_CRYPTO_0_CFG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CNOC_SLV_CRYPTO_1_CFG 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CNOC_SLV_IMEM_CFG 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CNOC_SLV_MESSAGE_RAM 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CNOC_SLV_BIMC_CFG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CNOC_SLV_BOOT_ROM 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CNOC_SLV_PMIC_ARB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CNOC_SLV_SPDM_WRAPPER 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CNOC_SLV_DEHR_CFG 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CNOC_SLV_MPM 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CNOC_SLV_QDSS_CFG 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CNOC_SLV_RBCPR_CFG 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CNOC_SLV_RBCPR_QDSS_APU_CFG 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CNOC_TO_SNOC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CNOC_SLV_CNOC_ONOC_CFG 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CNOC_SLV_CNOC_MNOC_MMSS_CFG 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CNOC_SLV_CNOC_MNOC_CFG 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CNOC_SLV_PNOC_CFG 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CNOC_SLV_SNOC_MPU_CFG 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CNOC_SLV_SNOC_CFG 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CNOC_SLV_EBI1_DLL_CFG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CNOC_SLV_PHY_APU_CFG 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CNOC_SLV_EBI1_PHY_CFG 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CNOC_SLV_RPM 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CNOC_SLV_SERVICE_CNOC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MNOC_MAS_GRAPHICS_3D 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MNOC_MAS_JPEG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MNOC_MAS_MDP_PORT0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MNOC_MAS_VIDEO_P0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MNOC_MAS_VIDEO_P1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MNOC_MAS_VFE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MNOC_TO_CNOC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MNOC_TO_BIMC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MNOC_SLV_CAMERA_CFG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MNOC_SLV_DISPLAY_CFG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MNOC_SLV_OCMEM_CFG 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MNOC_SLV_CPR_CFG 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MNOC_SLV_CPR_XPU_CFG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MNOC_SLV_MISC_CFG 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MNOC_SLV_MISC_XPU_CFG 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MNOC_SLV_VENUS_CFG 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MNOC_SLV_GRAPHICS_3D_CFG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MNOC_SLV_MMSS_CLK_CFG 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MNOC_SLV_MMSS_CLK_XPU_CFG 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MNOC_SLV_MNOC_MPU_CFG 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MNOC_SLV_ONOC_MPU_CFG 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MNOC_SLV_SERVICE_MNOC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OCMEM_NOC_TO_OCMEM_VNOC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OCMEM_MAS_JPEG_OCMEM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OCMEM_MAS_MDP_OCMEM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OCMEM_MAS_VIDEO_P0_OCMEM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OCMEM_MAS_VIDEO_P1_OCMEM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OCMEM_MAS_VFE_OCMEM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OCMEM_MAS_CNOC_ONOC_CFG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OCMEM_SLV_SERVICE_ONOC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OCMEM_VNOC_TO_SNOC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OCMEM_VNOC_TO_OCMEM_NOC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OCMEM_VNOC_MAS_GFX3D 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OCMEM_SLV_OCMEM 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PNOC_MAS_PNOC_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PNOC_MAS_SDCC_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PNOC_MAS_SDCC_3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PNOC_MAS_SDCC_4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PNOC_MAS_SDCC_2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PNOC_MAS_TSIF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PNOC_MAS_BAM_DMA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PNOC_MAS_BLSP_2 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PNOC_MAS_USB_HSIC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PNOC_MAS_BLSP_1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PNOC_MAS_USB_HS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PNOC_TO_SNOC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PNOC_SLV_SDCC_1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PNOC_SLV_SDCC_3 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PNOC_SLV_SDCC_2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PNOC_SLV_SDCC_4 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PNOC_SLV_TSIF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PNOC_SLV_BAM_DMA 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PNOC_SLV_BLSP_2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PNOC_SLV_USB_HSIC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PNOC_SLV_BLSP_1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PNOC_SLV_USB_HS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PNOC_SLV_PDM 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PNOC_SLV_PERIPH_APU_CFG 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PNOC_SLV_PNOC_MPU_CFG 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PNOC_SLV_PRNG 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PNOC_SLV_SERVICE_PNOC 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SNOC_MAS_LPASS_AHB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SNOC_MAS_QDSS_BAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SNOC_MAS_SNOC_CFG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SNOC_TO_BIMC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SNOC_TO_CNOC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SNOC_TO_PNOC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SNOC_TO_OCMEM_VNOC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SNOC_MAS_CRYPTO_CORE0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SNOC_MAS_CRYPTO_CORE1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SNOC_MAS_LPASS_PROC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SNOC_MAS_MSS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SNOC_MAS_MSS_NAV 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SNOC_MAS_OCMEM_DMA 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SNOC_MAS_WCSS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SNOC_MAS_QDSS_ETR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SNOC_MAS_USB3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SNOC_SLV_AMPSS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SNOC_SLV_LPASS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SNOC_SLV_USB3 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SNOC_SLV_WCSS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SNOC_SLV_OCIMEM 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SNOC_SLV_SNOC_OCMEM 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SNOC_SLV_SERVICE_SNOC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SNOC_SLV_QDSS_STM 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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