^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm interconnect IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019, Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Georgi Djakov <georgi.djakov@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BIMC_SNOC_SLV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MASTER_JPEG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MASTER_MDP_PORT0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MASTER_QDSS_BAM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MASTER_QDSS_ETR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MASTER_SNOC_CFG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MASTER_VFE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MASTER_VIDEO_P0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SNOC_MM_INT_0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SNOC_MM_INT_1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SNOC_MM_INT_2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SNOC_MM_INT_BIMC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCNOC_SNOC_SLV 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SLAVE_APSS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SLAVE_CATS_128 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SLAVE_OCMEM_64 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SLAVE_IMEM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SLAVE_QDSS_STM 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SLAVE_SRVC_SNOC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SNOC_BIMC_0_MAS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SNOC_BIMC_1_MAS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SNOC_INT_0 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SNOC_INT_1 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SNOC_INT_BIMC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SNOC_PCNOC_MAS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SNOC_QDSS_INT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BIMC_SNOC_MAS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MASTER_AMPSS_M0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MASTER_GRAPHICS_3D 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MASTER_TCU0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MASTER_TCU1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SLAVE_AMPSS_L2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SLAVE_EBI_CH0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SNOC_BIMC_0_SLV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SNOC_BIMC_1_SLV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MASTER_BLSP_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MASTER_DEHR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MASTER_LPASS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MASTER_CRYPTO_CORE0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MASTER_SDCC_1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MASTER_SDCC_2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MASTER_SPDM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MASTER_USB_HS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCNOC_INT_0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCNOC_INT_1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCNOC_MAS_0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCNOC_MAS_1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCNOC_SLV_0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCNOC_SLV_1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCNOC_SLV_2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCNOC_SLV_3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCNOC_SLV_4 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCNOC_SLV_8 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCNOC_SLV_9 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCNOC_SNOC_MAS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SLAVE_BIMC_CFG 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SLAVE_BLSP_1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SLAVE_BOOT_ROM 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SLAVE_CAMERA_CFG 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SLAVE_CLK_CTL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SLAVE_CRYPTO_0_CFG 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SLAVE_DEHR_CFG 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SLAVE_DISPLAY_CFG 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SLAVE_GRAPHICS_3D_CFG 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SLAVE_IMEM_CFG 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SLAVE_LPASS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SLAVE_MPM 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SLAVE_MSG_RAM 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SLAVE_MSS 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SLAVE_PDM 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SLAVE_PMIC_ARB 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SLAVE_PCNOC_CFG 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SLAVE_PRNG 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SLAVE_QDSS_CFG 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SLAVE_RBCPR_CFG 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SLAVE_SDCC_1 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SLAVE_SDCC_2 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SLAVE_SECURITY 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SLAVE_SNOC_CFG 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SLAVE_SPDM 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SLAVE_TCSR 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SLAVE_TLMM 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SLAVE_USB_HS 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SLAVE_VENUS_CFG 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SNOC_PCNOC_SLV 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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